HD151TS201ATEL RENESAS [Renesas Technology Corp], HD151TS201ATEL Datasheet - Page 12

• Manufacturer Part Number: HD151TS201ATEL
• Description: Mother Board Clock Generator for Intel P4 Chipset Banias and Dothan processor / ODEM and MONTARA-GM chip set
• Manufacturer: RENESAS [Renesas Technology Corp]

HD151TS201AT
I
Byte10 PLL N Divide Ratio Control Register
Bit
7
6
5
4
3
2
1
0
Note: The default N value will be reflected in S [2:0] or Byte8 bit[5:1] frequency setting value.
Byte11 PLL M Divide Ratio Control Register
Bit
7
6
5
4
3
2
1
0
Note: The default M value will be reflected in S [2:0] or Byte8 bit[5:1] frequency setting value.
Rev.1.00, Oct.21.2003, page 12 of 28
2
C Controlled Register Bit Map (cont.)
Byte9 [1:0], Byte10 and Byte11must be written together (at writing Byte11) in every case.
Byte9 [1:0], Byte10 and Byte11must be written together (at writing Byte11) in every case.
Description
PLL N Divider Control bit7
PLL N Divider Control bit6
PLL N Divider Control bit5
PLL N Divider Control bit4
PLL N Divider Control bit3
PLL N Divider Control bit2
PLL N Divider Control bit1
PLL N Divider Control bit0
Description
N & M divider enable bit
PLL M Divider Control bit6
PLL M Divider Control bit5
PLL M Divider Control bit4
PLL M Divider Control bit3
PLL M Divider Control bit2
PLL M Divider Control bit1
PLL M Divider Control bit0
Contents
PLL N Divider Control bit7
PLL N Divider Control bit6
PLL N Divider Control bit5
PLL N Divider Control bit4
PLL N Divider Control bit3
PLL N Divider Control bit2
PLL N Divider Control bit1
PLL N Divider Control bit0
Contents
0: N & M value will be determined by S [2:0] or
Byte8 bit[5:1].
1: N & M value will be determined by
Byte9,10,11.
PLL M Divider Control bit6
PLL M Divider Control bit5
PLL M Divider Control bit4
PLL M Divider Control bit3
PLL M Divider Control bit2
PLL M Divider Control bit1
PLL M Divider Control bit0
Default
Default
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X