AT24HC02B-10PU-1.8 ATMEL [ATMEL Corporation], AT24HC02B-10PU-1.8 Datasheet - Page 6

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AT24HC02B-10PU-1.8

Manufacturer Part Number
AT24HC02B-10PU-1.8
Description
Utilizes Different Array Protection Compared
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 2). Data changes during SCL high periods will indicate a start or stop condition as
defined below.
Figure 2. Data Validity
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
that must precede any other command (see Figure 3).
Figure 3. Start and Stop Definition
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 3).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
.
the EEPROM in 8-bit words.
The EEPROM sends a “0” to acknowledge that it has
received each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24HC02B features a low-power standby mode that is
enabled: (a) upon power-up and (b) after the receipt of the Stop bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any
two-wire part can be reset by following these steps:
AT24HC02B
6
5134A–SEEPR–9/05

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