AT24HC02B-10PU-1.8 ATMEL [ATMEL Corporation], AT24HC02B-10PU-1.8 Datasheet - Page 9

• Manufacturer Part Number: AT24HC02B-10PU-1.8
• Description: Utilizes Different Array Protection Compared
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 9. Page Write
5134A–SEEPR–9/05
SDA LINE
R
S
T
A
T
M
S
B
ADDRESS
DEVICE
L
S
B
W
W
R
E
R
T
I
/
Figure 8. Byte Write
PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send
a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to seven
(2K) more data words. The EEPROM will respond with a “0” after each data word
received. The microcontroller must terminate the page write sequence with a stop condi-
tion, see Figure 9.
The data word address lower three (2K) bits are internally incremented following the
receipt of each data word. The higher data word address bits are not incremented,
retaining the memory page row location. When the word address, internally generated,
reaches the page boundary, the following byte is placed at the beginning of the same
page. If more than eight (2K) data words are transmitted to the EEPROM, the data word
address will “roll over” and previous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a “0” allowing the read or write sequence to continue.
A
C
K
WORD ADDRESS (n)
SDA LINE
S
T
A
R
T
M
S
B
A
C
K
ADDRESS
DEVICE
DATA (n)
L
S
B
W
W
R
E
R
T
I
/
A
C
K
M
WORD ADDRESS
S
B
C
A
K
DATA (n + 1)
S
B
L
A
C
K
A
C
K
AT24HC02B
DATA
DATA (n + x)
C
A
K
S
O
P
T
A
C
K
O
S
T
P
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