AT25DF641A-MH-T ATMEL [ATMEL Corporation], AT25DF641A-MH-T Datasheet - Page 15

• Manufacturer Part Number: AT25DF641A-MH-T
• Description: 64-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

8.4
8693A–DFLASH–8/10
Chip Erase
Since the Block Erase command erases a region of bytes, the lower order address bits do not
need to be decoded by the device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be
ignored by the device and their values can be either a logical “1” or “0”. For a 32-Kbyte erase,
address bits A14-A0 will be ignored, and for a 64-Kbyte erase, address bits A15-A0 will be
ignored by the device. Despite the lower order address bits not being decoded by the device, the
complete three address bytes must still be clocked into the device before the CS pin is deas-
serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);
otherwise, the device will abort the operation and no erase operation will be performed.
If the address specified by A23-A0 points to a memory location within a sector that is in the pro-
tected or locked down state, then the Block Erase command will not be executed, and the device
will return to the idle state once the CS pin has been deasserted.
The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle
aborts due to an incomplete address being sent, the CS pin being deasserted on uneven byte
boundaries, or because a memory location within the region to be erased is protected or locked
down.
While the device is executing a successful erase cycle, the Status Register can be read and will
indicate that the device is busy. For faster throughput, it is recommended that the Status Regis-
ter be polled rather than waiting the t
some point before the erase cycle completes, the WEL bit in the Status Register will be reset
back to the logical “0” state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location
fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the Status
Register.
Figure 8-5.
The entire memory array can be erased in a single operation by using the Chip Erase command.
Before a Chip Erase command can be started, the Write Enable command must have been pre-
viously issued to the device to set the WEL bit of the Status Register to a logical “1” state.
Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in
device functionality when utilizing the two opcodes, so they can be used interchangeably. To
perform a Chip Erase, one of the two opcodes (60h or C7h) must be clocked into the device.
Since the entire memory array is to be erased, no address bytes need to be clocked into the
device, and any data clocked in after the opcode will be ignored. When the CS pin is deas-
serted, the device will erase the entire memory array. The erasing of the device is internally self-
timed and should take place in a time of t
SCK
SO
CS
SI
Block Erase
HIGH-IMPEDANCE
MSB
C
0
C
1
C
2
OPCODE
C
3
Atmel AT25DF641A [Preliminary]
C
4
BLKE
C
5
C
6
CHPE
time to determine if the device has finished erasing. At
C
7
MSB
A
8
.
A
9
A
10 11
A
ADDRESS BITS A23-A0
A
12
A
A
26
A
27 28
A
A
29 30
A
A
31
15