AT25DF641A-MH-T ATMEL [ATMEL Corporation], AT25DF641A-MH-T Datasheet - Page 33

• Manufacturer Part Number: AT25DF641A-MH-T
• Description: 64-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

10.5
Figure 10-5. Read OTP Security Register
11. Status Register Commands
11.1
8693A–DFLASH–8/10
SCK
SO
CS
SI
Read OTP Security Register
Read Status Register
MSB
HIGH-IMPEDANCE
0
0
1
1
1
2
OPCODE
1
3
0
The OTP Security Register can be sequentially read in a similar fashion to the Read Array oper-
ation up to the maximum clock frequency specified by f
the CS pin must first be asserted and the opcode of 77h must be clocked into the device. After
the opcode has been clocked in, the three address bytes must be clocked in to specify the start-
ing address location of the first byte to read within the OTP Security Register. Following the
three address bytes, two dummy bytes must be clocked into the device before data can be
output.
After the three address bytes and the dummy bytes have been clocked in, additional clock
cycles will result in OTP Security Register data being output on the SO pin. When the last byte
(00007Fh) of the OTP Security Register has been read, the device will continue reading back at
the beginning of the register (000000h). No delays will be incurred when wrapping around from
the end of the register to the beginning of the register.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-
ance state. The CS pin can be deasserted at any time and does not require that a full byte of
data be read.
The 2-byte Status Register can be read to determine the device’s ready/busy status, as well as
the status of many other functions such as Hardware Locking and Software Protection. The Sta-
tus Register can be read at any time, including during an internally self-timed program or erase
operation.
To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be
clocked into the device. After the opcode has been clocked in, the device will begin outputting
Status Register data on the SO pin during every subsequent clock cycle. After the second byte
of the Status Register has been clocked out, the sequence will repeat itself starting again with
the first byte of the Status Register as long as the CS pin remains asserted and the clock pin is
being pulsed. The data in the Status Register is constantly being updated, so each repeating
sequence will output new data. The RDY/BSY status is available for both bytes of the Status
Register and is updated for each byte.
4
1
5
1
6
1
7
MSB
A
8
A
9
ADDRESS BITS A23-A0
A
10 11
A
A
12
A
A
29 30
A
Atmel AT25DF641A [Preliminary]
A
31 32
MSB
X
X
33
X
34
X
DON'T CARE
35
X
36
X
MAX
X
. To read the OTP Security Register,
X
X
MSB
D
D
DATA BYTE 1
D
D
D
D
D
D
MSB
D
D
33