AT25DF641A-MH-T ATMEL [ATMEL Corporation], AT25DF641A-MH-T Datasheet - Page 5

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AT25DF641A-MH-T

Manufacturer Part Number
AT25DF641A-MH-T
Description
64-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
3. Block Diagram
Figure 3-1.
4. Memory Array
8693A–DFLASH–8/10
SO (SOI)
SI (SIO)
HOLD
SCK
WP
CS
Block Diagram
INTERFACE
CONTROL
To provide the greatest flexibility, the memory array of the Atmel
in four levels of granularity including a full chip erase. In addition, the array has been divided into
physical sectors of uniform size, of which each sector can be individually protected from pro-
gram and erase operations. The size of the physical sectors is optimized for both code and data
storage applications, allowing both code and data segments to reside in their own isolated
regions. The Memory Architecture Diagram illustrates the breakdown of each erase level as well
as the breakdown of each physical sector.
LOGIC
AND
PROTECTION LOGIC
CONTROL AND
Atmel AT25DF641A [Preliminary]
Y-DECODER
X-DECODER
®
AND LATCHES
MEMORY
I/O BUFFERS
AT25DF641A can be erased
Y-GATING
ARRAY
FLASH
DATA BUFFER
SRAM
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