M24128-BFBN3G STMICROELECTRONICS [STMicroelectronics], M24128-BFBN3G Datasheet - Page 26

• Manufacturer Part Number: M24128-BFBN3G
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

DC and AC parameters
26/39
Table 17.
1. Values recommended by the I²C-bus Fast-Mode specification.
2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
3. t
4. For a reStart condition, or following a Write cycle.
5. For production lots assembled from 1st July 2007 (data code 727: week27, year 2007), the M24xxx-R
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
C
CHCL
CLCH
XH1XH2
XL1XL2
DL1DL2
DXCX
CLDX
CLQX
CLQV
CHDX
DLCL
CHDH
DHDL
W
Symbol
rising edge of SDA.
compatible way with the I
× C
(1.8 V to 5.5 V range) memories are specified with t
CLQV
(2)(3)
(4)
bus
(1)
(1)
is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8V
time constant is less than 500 ns (as specified in
t
t
t
t
t
SU:STO
SU:DAT
HD:DAT
HD:STA
SU:STA
AC characteristics (M24xxx-W6, M24xxW3, M24xxR6)
t
t
f
t
HIGH
Alt.
LOW
t
t
SCL
BUF
DH
t
t
t
AA
R
F
F
Clock frequency
Clock pulse width high
Clock pulse width low
Input signal rise time
Input signal fall time
SDA (out) fall time
Data in set up time
Data in hold time
Data out hold time
Clock low to next data valid (access time)
Start condition set up time
Start condition hold time
Stop condition set up time
Time between Stop condition and next Start
condition
Write time
Test conditions specified in
2
C specification (which specifies t
Parameter
W
= 5 ms (instead of 10ms).
Figure
Table 8
SU:DAT
5).
(min) = 100 ns), assuming that the R
and
Table 9
M24128, M24C64, M24C32
1300
1300
Min.
600
200
600
600
100
200
600
20
20
20
0
Max.
400
300
300
100
900
5
CC
(5)
in a
Unit
kHz
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
bus