M24256-BF STMICROELECTRONICS [STMicroelectronics], M24256-BF Datasheet - Page 20

• Manufacturer Part Number: M24256-BF
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Device operation
3.13
3.14
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Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
Figure 11. Read mode sequences
Random Address Read (in memory array)
A dummy Write is first performed to load the address into this address counter (as shown in
Figure
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
Current
Address
Read
Random
Address
Read
Sequential
Current
Read
Sequential
Random
Read
11) but without sending a Stop condition. Then, the bus master sends another Start
Dev sel *
Dev sel *
ACK
Dev sel
Dev sel
Data out N
R/W
R/W
R/W
ACK
ACK
ACK
ACK
R/W
Doc ID 6757 Rev 21
NO ACK
Data out 1
Byte addr
Byte addr
Data out
M24256-BF, M24256-BR, M24256-BW, M24256-DR
NO ACK
ACK
ACK
ACK
Byte addr
Byte addr
ACK
ACK
ACK
Data out N
Dev sel *
Dev sel *
NO ACK
R/W
ACK
ACK
R/W
Data out 1
Data out
AI01105d
NO ACK
ACK