M24M01-S STMICROELECTRONICS [STMicroelectronics], M24M01-S Datasheet - Page 8

• Manufacturer Part Number: M24M01-S
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M24M01
Figure 8. Write Cycle Polling Flowchart using ACK
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
The maximum Write time (t
12, but the typical time is shorter. To make use of
this, a polling sequence can be used by the bus
master.
The sequence, as shown in Figure 8, is:
– Initial condition: a Write cycle is in progress.
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First byte of instruction
with RW = 0 already
decoded by the device
ReSTART
STOP
w
NO
) is shown in Table
NO
DEVICE SELECT
START Condition
WRITE Cycle
Addressing the
in Progress
with RW = 0
Operation is
Returned
Memory
ACK
Next
YES
WRITE Operation
WRITE Operation
DATA for the
Continue the
YES
NO
– Step 1: the bus master issues a Start condition
– Step 2: if the device is busy with the internal
followed by a Device Select Code (the first byte
of the new instruction).
Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the instruction (the
first byte of this instruction having been sent
during Step 1).
and Receive ACK
Send Address
Condition
START
Random READ Operation
DEVICE SELECT
Continue the
with RW = 1
YES
AI01847C