M24M01-S STMICROELECTRONICS [STMicroelectronics], M24M01-S Datasheet - Page 9

• Manufacturer Part Number: M24M01-S
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Figure 9. Read Mode Sequences
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
Random Address Read
A dummy Write is performed to load the address
into the address counter (as shown in Figure 9) but
without sending a Stop condition. Then, the bus
master sends another Start condition, and repeats
the Device Select Code, with the RW bit set to 1.
The device acknowledges this, and outputs the
contents of the addressed byte. The bus master
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
DEV SEL *
DEV SEL *
DEV SEL
DEV SEL
ACK
DATA OUT N
R/W
R/W
R/W
ACK
ACK
ACK
ACK
R/W
NO ACK
DATA OUT 1
BYTE ADDR
BYTE ADDR
DATA OUT
NO ACK
ACK
ACK
ACK
BYTE ADDR
BYTE ADDR
must not acknowledge the byte, and terminates
the transfer with a Stop condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read operation, following a Start
condition, the bus master only sends a Device Se-
lect Code with the RW bit set to 1. The device ac-
knowledges this, and outputs the byte addressed
by the internal address counter. The counter is
then incremented. The bus master terminates the
ACK
ACK
ACK
DATA OUT N
DEV SEL *
DEV SEL *
st
and 4
NO ACK
R/W
ACK
ACK
R/W
th
bytes) must be identical.
DATA OUT 1
DATA OUT
NO ACK
ACK
AI01105C
M24M01
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