M24C64-W STMICROELECTRONICS [STMicroelectronics], M24C64-W Datasheet - Page 19

• Manufacturer Part Number: M24C64-W
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M24C64-W M24C64-R M24C64-F M24C64-DF
5.1.6
Minimizing Write delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (t
shown in AC characteristics tables in
is shorter. To make use of this, a polling sequence can be used by the bus master.
The sequence, as shown in
●
●
●
Figure 10. Write cycle polling flowchart using ACK
1. The seven most significant bits of the Device Select code of a Random Read (bottom right box in the
First byte of instruction
with RW = 0 already
decoded by the device
figure) must be identical to the seven most significant bits of the Device Select code of the Write (polling
instruction in the figure).
Initial condition: a Write cycle is in progress.
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
ReStart
Stop
NO
Figure
NO
Doc ID 16891 Rev 27
Start condition
Device select
addressing the
with RW = 0
Operation is
in progress
Write cycle
returned
memory
ACK
Next
10, is:
Section 8: DC and AC
YES
Write cperation
Write operation
Continue the
Data for the
YES
NO
and Receive ACK
StartCondition
Send Address
parameters, but the typical time
Random Read operation
Device select
Continue the
with RW = 1
YES
Instructions
AI01847d
AI01847e
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) is
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