M28W320ECB70N6E STMICROELECTRONICS [STMicroelectronics], M28W320ECB70N6E Datasheet
M28W320ECB70N6E
Related parts for M28W320ECB70N6E
M28W320ECB70N6E Summary of contents
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... PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code, M28W320ECT: 88BAh – Bottom Device Code, M28W320ECB: 88BBh April 2003 M28W320ECT M28W320ECB 32 Mbit (2Mb x16, Boot Block) 3V Supply Flash Memory Figure 1. Packages FBGA TFBGA47 (ZB) 6.39 x 6.37mm TSOP48 ( 20mm 1/53 ...
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... SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. TSOP Connections Figure 4. TFBGA Connections (Top view through package Figure 5. Block Addresses Figure 6. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Address Inputs (A0-A20 Data Input/Output (DQ0-DQ15 Chip Enable (E Output Enable (G Write Enable (W Write Protect (WP) ...
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Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M28W320ECT, M28W320ECB PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The memory is offered in TSOP48 (10 X 20mm) and TFBGA47 (6.39 x 6.37mm, 0.75mm pitch) packages and is supplied with all the bits erased (set to ’1’). ...
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M28W320ECT, M28W320ECB Figure 3. TSOP Connections 6/53 A15 1 48 A14 A13 A12 A11 A10 A20 M28W320ECT M28W320ECB A19 A18 A17 ...
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Figure 4. TFBGA Connections (Top view through package A13 A14 B C A15 D A16 E V DDQ A11 A10 W RP A18 A12 A9 A20 DQ14 ...
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... KWords 008000 007FFF 32 KWords 000000 Note: Also see Appendix A, Tables 24 and 25 for a full listing of the Block Addresses. Figure 6. Protection Register Memory Map 8Ch 85h 84h 81h 80h Note1. Bit 2 of the Protection Register Lock must not be programmed to 0. 8/53 Bottom Boot Block Addresses ...
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... Register and Protection Register Lock). Reset (RP). The Reset input provides a hard- ware reset of the memory. When Reset the memory is in reset mode: the outputs are high impedance and the current consumption is mini- mized. After Reset all blocks are in the Locked state ...
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... Disable, Standby, Automatic Standby and Re- set. See Table 2, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Read. Read Bus operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface ...
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... COMMAND INTERFACE All Bus Write operations to the memory are inter- preted by the Command Interface. Commands consist of one or more sequential Bus Write oper- ations. An internal Program/Erase Controller han- dles all timings and verifies the correct execution of the Program and Erase commands. The Pro- ...
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... Read operations output the Status Register con- tent after the programming has started. Program- ming aborts if Reset goes to V cannot be guaranteed when the program opera- tion is aborted, the block containing the memory location must be erased and reprogrammed. See Appendix C, Figure 18, Double Word Pro data integrity ...
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... The segment can be protected by programming bit 1 of the Protection Lock Register (see Figure 6, M28W320ECT, M28W320ECB Protection Register Memory Map). Attempting to program a previously protected Protection Regis- ter will result in a Status Register error. The pro- tection of the Protection Register is not reversible. ...
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... The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on Table 4. Commands Commands 1st Cycle Op. Add Data Read Memory 1+ Write X Array Read Status 1+ Write X Register ...
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Table 5. Read Electronic Signature Code Device Manufacture. Code M28W320ECT Device Code M28W320ECB Note Table 6. Read Block Lock Signature Block Status Locked Block Unlocked Block IL ...
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M28W320ECT, M28W320ECB Table 8. Program, Erase Times and Program/Erase Endurance Cycles Parameter Word Program Double Word Program Quadruple Word Program Main Block Program Parameter Block Program Main Block Erase Parameter Block Erase Program/Erase Cycles (per Block) Data Retention Note: 1. ...
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BLOCK LOCKING The M28W320EC features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. Lock/Unlock - this first level allows software- only control ...
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M28W320ECT, M28W320ECB Table 9. Block Lock Status Item Block Lock Configuration Block is Unlocked Block is Locked Block is Locked-Down Table 10. Protection Status Current (1) Protection Status (WP, DQ1, DQ0) Program/Erase Current State Allowed 1,0,0 yes (2) no 1,0,1 ...
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... When the Erase Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Pro- gram/Erase Resume command. The Erase Suspend Status should only be consid- ered valid when the Program/Erase Controller Sta- tus bit is High (Program/Erase Controller inactive). Bit 7 is set within 30µ ...
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... Controller Status bit is High (Program/ Erase Controller inactive). Bit 2 is set within 5µs of the Program/Erase Suspend command being is- sued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is is- sued the Program Suspend Status bit returns Low. ...
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MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause per- manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above ...
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M28W320ECT, M28W320ECB DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC characteristics Tables that follow, are de- rived from ...
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Table 15. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current (Read) DD Supply Current (Stand- DD1 Automatic Stand-by) Supply Current I DD2 (Reset) I Supply Current (Program) DD3 I ...
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M28W320ECT, M28W320ECB Figure 9. Read AC Waveforms A0-A20 E G DQ0-DQ15 ADDR. VALID CHIP ENABLE Table 16. Read AC Characteristics Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Output Valid AVQV ...
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Figure 10. Write AC Waveforms, Write Enable Controlled M28W320ECT, M28W320ECB 25/53 ...
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M28W320ECT, M28W320ECB Table 17. Write AC Characteristics, Write Enable Controlled Symbol Alt t t Write Cycle Time AVAV Address Valid to Write Enable High AVWH Data Valid to Write Enable High DVWH DS t ...
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Figure 11. Write AC Waveforms, Chip Enable Controlled M28W320ECT, M28W320ECB 27/53 ...
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M28W320ECT, M28W320ECB Table 18. Write AC Characteristics, Chip Enable Controlled Symbol Alt t t Write Cycle Time AVAV Address Valid to Chip Enable High AVEH Data Valid to Chip Enable High DVEH DS Chip ...
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Figure 12. Power-Up and Reset AC Waveforms tVDHPH VDD, VDDQ Table 19. Power-Up and Reset AC Characteristics Symbol Parameter t PHWL Reset High to Write Enable Low, Chip t PHEL Enable Low, Output Enable Low t ...
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M28W320ECT, M28W320ECB PACKAGE MECHANICAL Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline 20mm, Package Outline 1 N/2 TSOP-a Note: Drawing is not to scale. Table 20. TSOP48 - 48 lead Plastic Thin Small Outline ...
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Figure 14. TFBGA47 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline BALL "A1" A Note: Drawing is not to scale. Table 21. TFBGA47 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Package Mechanical ...
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M28W320ECT, M28W320ECB Figure 15. TFBGA47 Daisy Chain - Package Connections (Top view through package Figure 16. TFBGA47 Daisy Chain - PCB Connections proposal (Top view through package ...
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PART NUMBERING Table 22. Ordering Information Scheme Example: Device Type M28 Operating Voltage 2.7V to 3.6V 1.65V to 3.6V DD DDQ Device Function 320EC = 32 Mbit (2 Mb x16), Boot Block Array Matrix ...
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... E = Lead-Free Package, Standard Packing F = Lead-Free Package, Tape & Reel Packing Note:Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. ...
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APPENDIX A. BLOCK ADDRESS TABLES Table 24. Top Boot Block Addresses, M28W320ECT Size # Address Range (KWord 1FF000-1FFFFF 1 4 1FE000-1FEFFF 2 4 1FD000-1FDFFF 3 4 1FC000-1FCFFF 4 4 1FB000-1FBFFF 5 4 1FA000-1FAFFF 6 4 1F9000-1F9FFF 7 4 ...
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M28W320ECT, M28W320ECB Table 25. Bottom Boot Block Addresses, M28W320ECB Size # Address Range (KWord 1F8000-1FFFFF 69 32 1F0000-1F7FFF 68 32 1E8000-1EFFFF 67 32 1E0000-1E7FFF 66 32 1D8000-1DFFFF 65 32 1D0000-1D7FFF 64 32 1C8000-1CFFFF 63 32 1C0000-1C7FFF 62 32 ...
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... Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’. M28W320ECT, M28W320ECB structure is read from the memory. Tables 26, 27, 28, 29, 30 and 31 show the addresses used to re- trieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is writ- ten (see Table 31, Security Code area) ...
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M28W320ECT, M28W320ECB Table 28. CFI Query System Interface Information Offset Data V Logic Supply Minimum Program/Erase or Write voltage DD 1Bh 0027h V Logic Supply Maximum Program/Erase or Write voltage DD 1Ch 0036h V [Programming] Supply Minimum Program/Erase voltage PP ...
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Table 29. Device Geometry Definition Offset Word Data Mode 27h 0016h Device Size = 2 28h 0001h Flash Device Interface Code description 29h 0000h 2Ah 0003h Maximum number of bytes in multi-byte program or page = 2 2Bh 0000h Number ...
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M28W320ECT, M28W320ECB Table 30. Primary Algorithm-Specific Extended Query Table Offset Data ( 35h (P+0)h = 35h 0050h (P+1)h = 36h 0052h Primary Algorithm extended Query table unique ASCII string “PRI” (P+2)h = 37h 0049h (P+3)h = 38h 0031h ...
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Table 31. Security Code Area Offset Data 80h 00XX Protection Register Lock 81h XXXX 82h XXXX 64 bits: unique device number 83h XXXX 84h XXXX 85h XXXX 86h XXXX 87h XXXX 88h XXXX 128 bits: User Programmable OTP 89h XXXX ...
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... If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 42/53 program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0x40) ; /*or writeToFlash (any_address, 0x10 writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 ...
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... If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0. double_word_program_command (addressToProgram1, dataToProgram1, { writeToFlash (any_address, 0x30) ; writeToFlash (addressToProgram1, dataToProgram1) ; writeToFlash (addressToProgram2, dataToProgram2) ; /*Memory enters read status state after the Program command status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 Invalid if (status_register ...
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... Program command status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 Invalid if (status_register.b3==1) /*VPP invalid error */ Error (1, 2) error_handler ( ) ...
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Figure 20. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another address Write D0h Program Continues program_suspend_command ( ) ...
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... Note error is found, the Status Register must be cleared before further Program/Erase operations. 46/53 erase_command ( blockToErase ) { writeToFlash (any_address, 0x20) ; writeToFlash (blockToErase, 0xD0 only A12-A20 are significannt */ /* Memory enters read status state after the Erase Command */ do { status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 ...
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Figure 22. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock Write ...
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M28W320ECT, M28W320ECB Figure 23. Locking Operations Flowchart and Pseudo Code Start Write 60h Write 01h, D0h or 2Fh Write 90h Read Block Lock States Locking change confirmed? YES Write FFh End 48/53 locking_operation_command (address, lock_operation) { writeToFlash (any_address, 0x60) ; ...
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... Note: 1. Status check of b1 (Protected Block sequence error is found, the Status Register must be cleared before further Program/Erase Controller operations. protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (any_address, 0xC0) ; writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command status_register=readFlash (any_address must be toggled*/ } while (status_register.b7 ...
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M28W320ECT, M28W320ECB APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE Table 32. Write State Machine Current/Next, sheet Data Current SR Read When State bit 7 Array Read (FFh) Read Array “1” Array Read Array Prog.Setup Read “1” ...
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Table 33. Write State Machine Current/Next, sheet Current State Read Elect.Sg. (90h) Read Array Read Elect.Sg. Read CFI Query Read Status Read Elect.Sg. Read CFI Query Read Elect.Sg. Read Elect.Sg. Read CFI Query Read CFI Query Read ...
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M28W320ECT, M28W320ECB REVISION HISTORY Table 34. Document Revision History Date Version 10-Sep-2001 -01 06-Nov-2001 -02 17-Jun-2002 -03 03-Oct-2002 3.1 19-Feb-2003 3.2 29-Apr-2003 3.3 52/53 Revision Details First Issue V Maximum changed to 3.3V DDQ Commands Table, Read CFI Query Address ...
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. ...