M28W320ECB70N6E STMICROELECTRONICS [STMicroelectronics], M28W320ECB70N6E Datasheet - Page 5

• Manufacturer Part Number: M28W320ECB70N6E
• Description: 32 Mbit (2Mb x16, Boot Block) 3V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SUMMARY DESCRIPTION
The M28W320EC is a 32 Mbit (2 Mbit x 16) non-
volatile Flash memory that can be erased electri-
cally at the block level and programmed in-system
on a Word-by-Word basis. These operations can
be performed using a single low voltage (2.7 to
3.6V) supply. V
down to 1.65V. An optional 12V V
is provided to speed up customer programming.
The device features an asymmetrical blocked ar-
chitecture. The M28W320EC has an array of 71
blocks: 8 Parameter Blocks of 4 KWord and 63
Main Blocks of 32 KWord. M28W320ECT has the
Parameter Blocks at the top of the memory ad-
dress space while the M28W320ECB locates the
Parameter Blocks starting from the bottom. The
memory maps are shown in Figure 5, Block Ad-
dresses.
The M28W320EC features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
When V
program or erase. All blocks are locked at Power
Up.
Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be suspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
The device includes a Protection Register to in-
crease the protection of a system design. The Pro-
tection Register is divided into two segments, the
first is a 64 bit area which contains a unique device
number written by ST, while the second is a 128 bit
area, one-time-programmable by the user. The
user programmable segment can be permanently
protected. Figure 6, shows the Protection Register
Memory Map.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.
PP
V
PPLK
DDQ
all blocks are protected against
allows to drive the I/O pin
PP
power supply
The memory is offered in TSOP48 (10 X 20mm)
and TFBGA47 (6.39 x 6.37mm, 0.75mm pitch)
packages and is supplied with all the bits erased
(set to ’1’).
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A20
DQ0-DQ15
E
G
W
RP
WP
V
V
V
V
NC
DD
DDQ
PP
SS
A0-A20
WP
RP
W
G
E
21
M28W320ECT, M28W320ECB
Address Inputs
Data Input/Output
Chip Enable
Output Enable
Write Enable
Reset
Write Protect
Core Power Supply
Power Supply for
Input/Output
Optional Supply Voltage for
Fast Program & Erase
Ground
Not Connected Internally
V DD
M28W320ECT
M28W320ECB
V SS
V DDQ V PP
16
DQ0-DQ15
AI05517
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