NAND04GW3B2AN1F NUMONYX [Numonyx B.V], NAND04GW3B2AN1F Datasheet - Page 27

• Manufacturer Part Number: NAND04GW3B2AN1F
• Description: 4 Gbit, 8 Gbit, 2112 Byte/1056 Word Page 3V, NAND Flash Memories
• Manufacturer: NUMONYX [Numonyx B.V]

NAND04GW3B2B, NAND08GW3B2A
6.6
Figure 13. Block Erase Operation
6.7
RB
I/O
Block Erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of three steps (refer to
1.
2.
3.
The operation is initiated on the rising edge of write Enable, W, after the confirm command
is issued. The P/E/R Controller handles Block Erase and implements the verify process.
During the Block Erase operation, only the Read Status Register and Reset commands will
be accepted, all other commands will be ignored.
Once the program operation has completed the P/E/R Controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completed successfully, the Write Status Bit
SR0 is ‘0’, otherwise it is set to ‘1’.
Reset
The Reset command is used to reset the Command Interface and Status Register. If the
Reset command is issued during any operation, the operation will be aborted. If it was a
program or erase operation that was aborted, the contents of the memory locations being
modified will no longer be valid as the data will be partially programmed or erased.
If the device has already been reset then the new Reset command will not be accepted.
The Ready/Busy signal goes Low for t
of t
issued, refer to
Block Erase
Setup Code
BLBH4
One bus cycle is required to setup the Block Erase command. Only addresses A18-
A29 are used, the other address inputs are ignored.
Three bus cycles are then required to load the address of the block to be erased. Refer
to
One bus cycle is required to issue the Block Erase confirm command to start the P/E/R
Controller.
60h
Table 6: Address Definition
depends on the operation that the device was performing when the command was
Table 21
Block Address
Inputs
for the values.
for the block addresses of each device.
Confirm
Code
D0h
BLBH4
after the Reset command is issued. The value
(Erase Busy time)
Figure 13: Block Erase
tBLBH3
Busy
Read Status Register
70h
Device operations
Operation):
SR0
ai07593
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