CY14B101LA CYPRESS [Cypress Semiconductor], CY14B101LA Datasheet - Page 14

• Manufacturer Part Number: CY14B101LA
• Description: 1 Mbit (128K x 8/64K x 16) nvSRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 001-42879 Rev. *C
Software Controlled STORE/RECALL Cycle
Switching Waveforms
Notes
Parameters
t
t
t
t
t
27. The software sequence is clocked with CE controlled or OE controlled reads.
28. The six consecutive addresses must be read in the order listed in
29. DQ output data at the sixth read may be invalid since the output is disabled at t
RC
SA
CW
HA
RECALL
HSB (STORE only)
[27, 28]
DQ (DATA)
DQ (DATA)
Address
Address
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
RWI
OE
CE
CE
OE
t
Figure 12. CE and OE Controlled Software STORE/RECALL Cycle
SA
t
SA
t
LZCE
t
SA
t
Description
LZCE
t
Address #1
SA
Address #1
t
t
RC
CW
Figure 13. Autostore Enable/Disable Cycle
t
RC
t
CW
PRELIMINARY
t
HZCE
Table 2
t
t
HA
HA
t
t
HZCE
t
on page 5. WE must be HIGH during all six consecutive cycles.
HA
HA
DELAY
Min
20
15
t
0
0
DELAY
time.
20 ns
Address #6
Note
Max
200
t
RC
t
29
CW
t
HA
Address #6
CY14B101LA, CY14B101NA
High Impedance
Note
Min
t
25
20
t
STORE
RC
0
0
t
29
CW
25 ns
t
t
HA
HA
/t
RECALL
t
DELAY
t
Max
SS
200
[28]
t
HA
Min
45
30
0
0
45 ns
t
HHHD
Max
200
Page 14 of 24
t
LZHSB
Unit
ns
ns
ns
ns
µs
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