CY14B101LA CYPRESS [Cypress Semiconductor], CY14B101LA Datasheet - Page 3

• Manufacturer Part Number: CY14B101LA
• Description: 1 Mbit (128K x 8/64K x 16) nvSRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Pinouts
Table 1. Pin Definitions
Document #: 001-42879 Rev. *C
DQ
DQ
Pin Name
A
A
HSB
0
0
0
V
BHE
0
BLE
V
WE
V
CE
OE
NC
– A
– A
– DQ
CAP
– DQ
CC
SS
[8]
16
15
15
7
(continued)
Input/Output
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
No Connect No Connect. This pin is not connected to the die.
I/O Type
Ground
Supply
Supply
Power
Power
Input
Input
Input
Input
Input
Input
Address Inputs Used to Select one of the 131,072 Bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 65,536 Words of the nvSRAM for x16 Configuration.
Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on operation.
Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on
operation.
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tristated on deasserting OE HIGH.
Byte High Enable, Active LOW. Controls DQ
Byte Low Enable, Active LOW. Controls DQ
Ground for the Device. Must be connected to the ground of the system.
Power Supply Inputs to the Device. 3.0V +20%, –10%
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up
resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation HSB is
driven HIGH for short time with standard output high current.
AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Figure 3. Pin Diagram - 54-Pin TSOP II
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V
V
WE
NC
CE
NC
NC
NC
NC
CC
SS
A
A
A
A
A
A
A
A
A
A
[7]
0
1
2
3
4
0
1
2
3
4
5
6
7
5
6
7
8
9
PRELIMINARY
13
14
26
1
5
6
7
8
9
10
11
12
15
16
17
18
19
20
24
25
27
2
3
4
21
22
23
54 - TSOP II
(
Top View
not to scale)
(x16)
Description
7
49
48
47
41
40
39
37
36
35
34
33
32
29
28
50
46
45
44
43
42
38
31
30
15
54
53
52
51
- DQ
- DQ
HSB
BHE
DQ
DQ
DQ
DQ
NC
NC
NC
NC
NC
OE
BLE
DQ
V
A
A
NC
A
V
DQ
DQ
DQ
A
A
A
V
0
15
14
13
12
11
10
SS
CC
CAP
.
8
15
[5]
[4]
14
13
12
[6]
9
8
.
11
10
CY14B101LA, CY14B101NA
Page 3 of 24
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