LH28F160S5-L SHARP [Sharp Electrionic Components], LH28F160S5-L Datasheet - Page 33

• Manufacturer Part Number: LH28F160S5-L
• Description: 16 M-bit (2 MB x 8/1 MB x 16) Smart 5 Flash Memories (Fast Programming)
• Manufacturer: SHARP [Sharp Electrionic Components]

5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory
arrays. SHARP provides three control inputs to
accommodate multiple memory connections. Three-
line control provides for :
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while
deselected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2 STS and Block Erase, Full Chip
STS is an open drain output that should be
connected to V
hardware method of detecting block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration completion. In default mode, it
transitions low after block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration
commands and returns to V
finished executing the internal algorithm. For
alternate STS pin configurations, see the Configu-
ration command (Table 3 and Section 4.14).
STS can be connected to an interrupt input of the
system CPU or controller. It is active at all times.
STS, in default mode, is also High Z when the
device is in block erase suspend (with (multi)
word/byte write inactive), (multi) word/byte write
suspend or deep power-down modes.
a. Lowest possible memory power consumption.
b. Complete assurance that data bus contention
will not occur.
Erase, (Multi) Word/Byte Write and
Block Lock-Bit Configuration Polling
CC
by a pullup resistor to provide a
OH
when the WSM has
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5.3 Power Supply Decoupling
Flash memory power switching characteristics
require
designers are interested in three supply current
issues; standby current levels, active current levels
and transient peaks produced by falling and rising
edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’
capacitive and inductive loading. Two-line control
and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device
should have a 0.1 µF ceramic capacitor connected
between its V
and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7 µF electrolytic capacitor should be placed at
the array’s power supply connection between V
and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.
5.4 V
Updating flash memories that reside in the target
system requires that the printed circuit board
designers pay attention to the V
trace. The V
for block erase, full chip erase, (multi) word/byte
write and block lock-bit configuration. Use similar
trace widths and layout considerations given to the
V
decoupling will decrease V
overshoots.
5.5 V
Block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration are not guaranteed
if V
outside of a valid V
V
to "1" along with SR.4 or SR.5, depending on the
attempted operation. If RP# transitions to V
block erase, full chip erase, (multi) word/byte write
or block lock-bit configuration, STS (if set to
CC
PP
PP
error is detected, status register bit SR.3 is set
power bus. Adequate V
falls outside of a valid V
PP
CC
careful
, V
Trace on Printed Circuit Boards
PP
CC
PP
pin supplies the memory cell current
, RP# Transitions
and GND and between its V
device
CC1/2
LH28F160S5-L/S5H-L
range, or RP# = V
PP
decoupling.
PP
PPH1
voltage spikes and
supply traces and
PP
range, V
power supply
IL
System
CC
during
IL
falls
. If
CC
PP