S-93C46BD0I-I8T1G SII [Seiko Instruments Inc], S-93C46BD0I-I8T1G Datasheet - Page 16
S-93C46BD0I-I8T1G
Manufacturer Part Number
S-93C46BD0I-I8T1G
Description
3-WIRE SERIAL E2PROM
Manufacturer
SII [Seiko Instruments Inc]
Datasheet
1.S-93C46BD0I-I8T1G.pdf
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16
3-WIRE SERIAL E
S-93C46B/56B/66B
4. 4 Writing to chip (WRAL)
CS
SK
DO
DI
To write the same 16-bit data to the entire memory address space, change CS to high, and then input the
WRAL instruction, an address, and 16-bit data following the start bit. Any address can be input. The
write operation starts when CS goes low. There is no need to set the data to 1 before writing. If the clocks
more than the specified number have been input, the clock pulse monitoring circuit cancels the WRAL
instruction. For details of the clock pulse monitoring circuit, refer to “
Write due to Erroneous Instruction Recognition ”.
DO
CS
SK
DI
1
2
1
PROM
2
0
2
0
0
3
0
3
0
High-Z
Figure 16 Chip Write Timing (S-93C56B, S-93C66B)
0
4
High-Z
4
1
5
Figure 15 Chip Write Timing (S-93C46B)
1
5
Seiko Instruments Inc.
6
6
7
7
6Xs
8
4Xs
8
9
9
10
D15
10
11
D15
12
25
D0
t
SV
t
CDS
27
D0
Function to Protect Against
t
PR
t
SV
t
CDS
Verify
busy
t
PR
ready
Verify
busy
Rev.7.0
Standby
High-Z
ready
t
HZ1
_00
Standby
High-Z
t
HZ1
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