S-93C46BD0I-I8T1G SII [Seiko Instruments Inc], S-93C46BD0I-I8T1G Datasheet - Page 20

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S-93C46BD0I-I8T1G

Manufacturer Part Number
S-93C46BD0I-I8T1G
Description
3-WIRE SERIAL E2PROM
Manufacturer
SII [Seiko Instruments Inc]
Datasheet
20
3-WIRE SERIAL E
S-93C46B/56B/66B
Function to Protect Against Write due to Erroneous Instruction Recognition
The S-93C46B/56B/66B provides a built-in clock pulse monitoring circuit which is used to prevent an erroneous
write operation by canceling write instructions (WRITE, ERASE, WRAL, and ERAL) recognized erroneously due to
an erroneous clock count caused by the application of noise pulses or double counting of clocks.
Instructions are cancelled if a clock pulse more or less than specified number decided by each write operation
(WRITE, ERASE, WRAL, or ERAL) is detected.
<Example> Erroneous recognition of program disable instruction (EWDS) as erase instruction (ERASE)
Input EWDS instruction
Erroneous recognition as
ERASE instruction due to
noise pulse
Example of S-93C46B
In products that do not include a clock pulse monitoring circuit, FFFF is mistakenly written
on address 00h. However the S-93C46B detects the overcount and cancels the instruction
without performing a write operation.
2
PROM
Figure 22 Example of Clock Pulse Monitoring Circuit Operation
CS
SK
DI
Seiko Instruments Inc.
1
1
1
1
1
0
0
2
Noise pulse
0
0
3
0
0
4
0
0
0
5
0
0
6
0
0
7
0
0
8
0
0
9
Rev.7.0
_00

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