STK16C88-3_08 SIMTEK [Simtek Corporation], STK16C88-3_08 Datasheet - Page 4

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STK16C88-3_08

Manufacturer Part Number
STK16C88-3_08
Description
32Kx8 AutoStore+ nvSRAM
Manufacturer
SIMTEK [Simtek Corporation]
Datasheet
STK16C88-3
Document Control #ML0019 Rev 2.0
SRAM READ CYCLES #1 & #2
Note f:
Note g: I/O state assumes E, G < V
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled
SRAM READ CYCLE #2: E and G Controlled
DQ (DATA OUT)
NO.
10
11
DQ (DATA OUT)
1
2
3
4
5
6
7
8
9
Jan, 2008
ADDRESS
ADDRESS
t
AVEL
W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
27
t
t
t
t
t
t
t
t
t
t
t
ELQV
AVAV
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL
I
CC
G
E
f
,
g
g
h
h
t
ELEH
e
d
#1, #2
,
e
f
SYMBOLS
IL
and W > V
t
t
t
t
t
t
t
t
t
t
t
ACS
RC
AA
OE
OH
LZ
HZ
OLZ
OHZ
PA
PS
STANDBY
Alt.
t
ELICCH
t
t
IH
AXQX
10
ELQX
t
6
; device is continuously selected.
5
GLQX
8
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Address Change or Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
t
t
AVQV
GLQV
(V
3
4
CC
t
ELEH
2
t
t
ACTIVE
= 3.0V-3.6V)
AVQV
ELQV
1
3
4
t
AVAV
2
PARAMETER
f
f, g
DATA VALID
DATA VALID
t
GHQZ
STK16C88-3-35
MIN
9
35
5
5
0
0
t
EHQZ
7
t
EHICCL
11
MAX
35
35
15
13
13
35
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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