STK16C88-3_08 SIMTEK [Simtek Corporation], STK16C88-3_08 Datasheet - Page 8

• Manufacturer Part Number: STK16C88-3_08
• Description: 32Kx8 AutoStore+ nvSRAM
• Manufacturer: SIMTEK [Simtek Corporation]

STK16C88-3
Document Control #ML0019 Rev 2.0
The AutoStore+ STK16C88-3 is a fast 32K x 8
SRAM that does not lose its data on power-down.
The data is preserved in integral Quantum Trap non-
volatile storage elements when power is lost. Auto-
matic STORE on power-down and automatic
RECALL on power-up guarantee data integrity with-
out the use of batteries.
NOISE CONSIDERATIONS
Note that the STK16C88-3 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1μF connected between V
and V
possible. As with all high-speed
careful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
The STK16C88-3 performs a
E and G are low and W is high. The address speci-
fied on pins A
data bytes will be accessed. When the
ated by an address transition, the outputs will be
valid after a delay of t
READ
at t
The data outputs will repeatedly respond to address
changes within the t
for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high.
SRAM WRITE
A
low. The address inputs must be stable prior to
entering the
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ
ten into the memory if it is valid t
of a W controlled
E controlled
It is recommended that G be kept high during the
entire
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
WRITE
ELQV
Jan, 2008
SS
is initiated by E or G, the outputs will be valid
WRITE
or at t
, using leads and traces that are as short as
cycle is performed whenever E and W are
WRITE
GLQV
WRITE
cycle to avoid data bus contention on
0-14
, whichever is later (
WRITE
determines which of the 32,768
.
AVQV
cycle and must remain stable
AVQV
access time without the need
or t
DVEH
(
READ
WLQZ
READ
before the end of an
DVWH
CMOS
after W goes low.
cycle #1). If the
nvSRAM OPERATION
cycle whenever
READ
before the end
0-7
READ
ICs, normal
will be writ-
cycle #2).
is initi-
CC
8
AutoStore+ OPERATION
The STK16C88-3’s automatic
down is completely transparent to the system. The
STORE initiation takes less than 500ns when power
is lost (V
only on its internal capacitor for
If the power supply drops faster than 20μs/volt
before Vcc reaches Vswitch, then a 1 ohm resistor
should be inserted between Vcc and the system
supply to avoid a momentary excess of current
between Vcc and internal capacitor.
In order to prevent unneeded
automatic
one
recent
STORE
or not a
POWER-UP RECALL
During power up, or after any low-power condition
(V
latched. When V
voltage of V
be initiated and will take t
If the STK16C88-3 is in a
power-up
To help avoid this situation, a 10kΩ resistor should
be connected either between W and system V
between E and system V
SOFTWARE NONVOLATILE STORE
The STK16C88-3 software
by executing sequential
cific address locations. During the
vious nonvolatile data is erased and then the SRAM
contents are written to the nonvolatile storage ele-
ments. Once a
and output are disabled until the cycle is completed.
Because a sequence of
addresses is used for
tant that no other
vene in the sequence or the sequence will be
aborted and no
To initiate the software
READ
CC
WRITE
< V
sequence must be performed:
STORE
cycles are performed regardless of whether
WRITE
CC
RESET
RECALL
STORE
< V
operation has taken place since the most
SWITCH
), an internal
SWITCH
or
operation has taken place.
STORE
STORE
, a
CC
s will be ignored unless at least
, the
RECALL
READ
) at which point the part depends
once again exceeds the sense
RECALL
cycle is initiated, further input
SRAM
STORE
or
STORE
CC
READ
RESTORE
or
RECALL
WRITE
.
cycle. Software initiated
RECALL
STORE
WRITE
cycle will automatically
READ
data will be corrupted.
initiation, it is impor-
cycles from six spe-
STORE
to complete.
cycle, the following
STORE
STORE
state at the end of
STORE
will take place.
s from specific
cycle is initiated
accesses inter-
request will be
completion.
operations,
on power-
cycle, pre-
CC
or