X9521 XICOR [Xicor Inc.], X9521 Datasheet - Page 10

• Manufacturer Part Number: X9521
• Description: Dual DCP, EEPROM Memory
• Manufacturer: XICOR [Xicor Inc.]

The master terminates the Data Byte loading by issuing a
STOP condition, which causes the X9521 to begin the
nonvolatile write cycle. As with the byte write operation, all
inputs are disabled until completion of the internal write
cycle. See Figure 12 for the address, ACKNOWLEDGE,
and data transfer sequence.
Stops and EEPROM Write Modes
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
and receiving the subsequent ACKNOWLEDGE signal. If
the master issues a STOP within a Data Byte, or before
the X9521 issues a corresponding ACKNOWLEDGE, the
X9521 cancels the write operation. Therefore, the con-
tents of the EEPROM array does not change.
EEPROM Array Read Operations
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the Slave
Address Byte is set to one. There are three basic read
operations: Current EEPROM Address Read, Random
EEPROM Read, and Sequential EEPROM Read.
X9521 – Preliminary Information
REV 1.1.9 1/30/03
Figure 13. Example: Writing 12 bytes to a 16-byte page starting at location 11.
Figure 14. Current EEPROM Address Read Sequence
7 bytes
Signals from
the Master
SDA Bus
Signals from
the Slave
address
= 6
10
S
a
t
r
t
www.xicor.com
1 01 0 0 0 0
Address
Slave
address pointer
ends here
Addr = 7
Current EEPROM Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented
by one. Therefore, if the last read was to address n, the
next read operation would access data from address n+1.
On power up, the address of the address counter is unde-
fined, requiring a read or write operation for initialization.
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an ACKNOWLEDGE and
then transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond
with an ACKNOWLEDGE during the ninth clock and then
issues a STOP condition (See Figure 14 for the address,
ACKNOWLEDGE, and data transfer sequence).
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read opera-
tion, the master must either issue a STOP condition dur-
ing the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a STOP condition.
Another important point to note regarding the “Current
EEPROM Address Read” , is that this operation is not
available if the last executed operation was an access to a
DCP or the CONSTAT Register (i.e.: an operation using
1
10
A
C
K
address
11
Data
10
5 bytes
Characteristics subject to change without notice.
5 bytes
S
o
p
t
address
15
10
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