STM8S105C4B3 STMICROELECTRONICS [STMicroelectronics], STM8S105C4B3 Datasheet - Page 96
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STM8S105C4B3
Manufacturer Part Number
STM8S105C4B3
Description
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.STM8S105C4B3.pdf
(127 pages)
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Electrical characteristics
96/127
1. Measurement points are made at CMOS levels: 0.3 V
1. Measurement points are made at CMOS levels: 0.3 V
OUT P UT
NSS input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
I NPUT
MISO
MOSI
NSS input
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
OUTUT
INP UT
MISO
MOSI
Figure 42: SPI timing diagram - slave mode and CPHA = 1
t SU(NSS)
t a(SO)
High
t w(SCKH)
t w(SCKL)
t su(MI)
Figure 43: SPI timing diagram - master mode
t su(SI)
M SB OUT
M SB IN
DocID14771 Rev 9
t w(SCKH)
t w(SCKL)
MS B O UT
MS BIN
t v(MO)
t h(MI)
t c(SCK)
t v(SO)
t h(SI)
t c(SCK)
B I T1 OUT
BI T6 IN
t h(MO)
B I T1 IN
BI T6 OUT
t h(SO)
DD
DD
and 0.7 V
and 0.7 V
t r(SCK)
t f(SCK)
t h(NSS)
LSB OUT
LSB IN
t r(SCK)
t f(SCK)
LSB IN
(1)
LSB OUT
DD
DD
t dis(SO)
.
.
(1)
STM8S105xx
ai14136
ai14135
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