HIP6021A_01 INTERSIL [Intersil Corporation], HIP6021A_01 Datasheet - Page 12

• Manufacturer Part Number: HIP6021A_01
• Description: Advanced PWM and Triple Linear Power Controller
• Manufacturer: INTERSIL [Intersil Corporation]

Figure 9 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 8. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The gain. Check the compensation gain at F
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the log-log graph of Figure 9 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB). This
is equivalent to multiplying the modulator transfer function to
the compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
+5V
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
+3.3V
FB
V
FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES AND
V
+3.3V
OUT3
IN
OUT2
and Z
IN
IN
C
L
C
C
OUT3
IN
IN
OUT2
ST
ND
ST
ND
IN
to provide a stable, high bandwidth (BW)
ISLANDS
Q3
Zero Below Filter’s Double Pole (~75% F
Pole at the ESR Zero
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
C
Q4
SS
+12V
KEY
DRIVE2
SS
DRIVE3
VCC
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
HIP6021A
C
VCC
PGND
12
OCSET1
UGATE1
PHASE1
LGATE1
GND
DRIVE4
C
Q2
OCSET1
Q5
P2
Q1
with the
R
L
C
CR1
C
OUT1
OCSET1
OUT4
OUT1
V
OUT4
V
LC
OUT1
HIP6021A
)
Compensation Break Frequency Equations
F
F
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Z1
Z2
100
Δ
-20
-40
-60
FIGURE 8. VOLTAGE-MODE BUCK CONVERTER
80
60
40
20
V
0
=
=
OSC
-----------------------------------
2π R
------------------------------------------------------ -
2π
10
MODULATOR
20
OSC
×
×
log
(
R1
1
2
⎛
⎝
COMPENSATION DESIGN
100
R2
------- -
R1
ERROR
AMP
GAIN
DETAILED COMPENSATION COMPONENTS
×
V
F
HIP6021A
+
1
E/A
Z1
C1
COMP
⎞
⎠
PWM
R3
Z
+
-
COMP
)
FB
-
+
F
×
1K
LC
C1
C3
REFERENCE
F
FREQUENCY (Hz)
Z2
C2
DACOUT
+
-
F
R2
ESR
10K
DRIVER
DRIVER
F
F
Z
F
IN
P1
P2
P1
=
=
100K
FB
Z
F
------------------------------------------------------ -
2π
-----------------------------------
2π
V
FB
P2
IN
PHASE
×
×
(PARASITIC)
C3
R
R
1
1M
2
3
Z
R1
L
ERROR AMP GAIN
IN
×
×
O
1
⎛
⎝
COMPENSATION
C3
R3
ESR
C1
--------------------- -
C1
OPEN LOOP
CLOSED LOOP
GAIN
C
20
O
V
10M
log
OUT
×
+
GAIN
C2
C2
⎛
⎜
⎝
----------- -
V
V
V
⎞
⎠
PP
IN
OUT
⎞
⎟
⎠