HIP6021A_01 INTERSIL [Intersil Corporation], HIP6021A_01 Datasheet - Page 8

• Manufacturer Part Number: HIP6021A_01
• Description: Advanced PWM and Triple Linear Power Controller
• Manufacturer: INTERSIL [Intersil Corporation]

T2. During the interval between T2 and T3, the error
amplifier reference ramps to the final value and the
converter regulates the output a voltage proportional to the
SS pin voltage. At T3 the input clamp voltage exceeds the
reference voltage and the output voltage is in regulation.
The remaining outputs are also programmed to follow the
SS pin voltage. The PGOOD signal toggles ‘high’ when all
output voltage levels have exceeded their under-voltage
levels. The waveform for V
SELECT is held ‘high’. The AGP bus voltage is controlled in
the same manner as the other linear regulators during the
softstart sequence. Once the softstart sequence is
complete (T4), the gate of the external pass device is fully
enhanced and V
Soft-Start Interval section under Applications Guidelines for
a procedure to determine the soft-start interval.
Fault Protection
All four outputs are monitored and protected against extreme
overload. A sustained overload on any output or an over-
voltage on V
drives the FAULT/RT pin to VCC.
Figure 3 shows a simplified schematic of the fault logic. An
over-voltage detected on VSEN1 immediately sets the fault
latch. A sequence of three over-current fault signals also
sets the fault latch. The over-current latch is set dependent
upon the states of the over-current (OC), linear under-
voltage (LUV) and the soft-start signals. A window
comparator monitors the SS pin and indicates when C
fully charged to 4V (UP signal). An under-voltage on either
0V
0V
0V
VOLTAGES
(0.5V/DIV)
OUTPUT
T0
T1
OUT1
FIGURE 2. SOFT-START INTERVAL
SOFT-START
PGOOD
(1V/DIV)
OUT2
output (VSEN1) disables all outputs and
tracks the 3.3V
T2
OUT2
TIME
8
represents the case where
T3
IN
V
voltage. See the
OUT1
V
V
V
OUT2
OUT4
OUT3
(DAC = 2.5V)
(= 3.3V
(= 1.8V)
(= 1.5V)
T4
IN
SS
)
is
HIP6021A
linear output (VSEN2, VSEN3, or VSEN4) is ignored until
after the soft-start interval (T4 in Figure 2). This allows
V
up. Cycling the bias input voltage (+12V
then on) resets the counter and the fault latch.
Over-Voltage Protection
During operation, a short on the upper MOSFET of the PWM
regulator (Q1) causes V
exceeds the over-voltage threshold of 115% of DACOUT,
the over-voltage comparator trips to set the fault latch and
turns Q2 on. This blows the input fuse and reduces V
The fault latch raises the FAULT/RT pin to VCC.
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), the output level
is monitored for voltages above 1.3V. Should VSEN1
exceed this level, the lower MOSFET, Q2 is driven on.
Over-Current Protection
All outputs are protected against excessive over-currents.
The PWM controller uses the upper MOSFET’s
on-resistance, r
against shorted output. All linear controllers monitor their
respective VSEN pins for under-voltage events to protect
against excessive currents.
Figure 4 illustrates the over-current protection with an
overload on OUT1. The overload is applied at T0 and the
current increases through the inductor (L
the OVER-CURRENT comparator trips when the voltage
across Q1 (i
ROCSET. This inhibits all outputs, discharges the soft-start
capacitor (C
the counter. C
cycle with the error amplifiers clamped by soft-start. With
OUT1 still overloaded, the inductor current increases to trip
the over-current comparator. Again, this inhibits all outputs,
but the soft-start voltage continues increasing to 4V before
discharging. The counter increments to 2. The soft-start
cycle repeats at T3 and trips the over-current comparator.
OC1
LUV
OUT2
SS
OV
0.15V
FIGURE 3. FAULT LOGIC - SIMPLIFIED SCHEMATIC
4V
, V
OUT3
+
+
-
-
D
SS
SS
• r
) with a 10mA current sink, and increments
, and V
DS(ON)
DS(ON)
CURRENT
UP
recharges at T2 and initiates a soft-start
LATCH
OVER-
S
R
Q
OUT4
to monitor the current for protection
) exceeds the level programmed by
OUT1
POR
to increase without fault at start-
to increase. When the output
R
COUNTER
IN
OUT1
INHIBIT
on the VCC pin off
LATCH
FAULT
S
R
). At time T1,
Q
VCC
OUT1
FAULT
.