A29800TM-55 AMICC [AMIC Technology], A29800TM-55 Datasheet
A29800TM-55
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A29800TM-55 Summary of contents
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Preliminary Features n 5.0V 10% for read and write operations n Access times: - 55/70/90 (max.) n Current: - 28mA read current (word mode typical active read current (byte mode typical program/erase current - ...
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During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The host system can detect whether a program or erase operation is complete by reading the I/O I/O (toggle) status bits. After a program or ...
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Block Diagram RY/BY VCC VSS RESET State WE Control BYTE Command Register CE OE VCC Detector A0-A18 Pin Descriptions Pin No A18 I/O I/O (A-1) 15 RESET PRELIMINARY (May, 2001, Version 0.0) Sector Switches Erase Voltage Generator PGM ...
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Absolute Maximum Ratings* Ambient Operating Temperature . . . . . - 125 C Storage Temperature . . . . . . . . . . . . . . - 125 C Ground ...
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Word/Byte Configuration The BYTE pin determines whether the I/O pins I/O operate in the byte or word configuration. If the is set at logic ”1”, the device is in word configuration, I/O I/O are active and controlled ...
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Table 2. A29800 Top Boot Block Sector Address Table Sector A18 A17 A16 A15 SA0 SA1 SA2 SA3 SA4 SA5 SA6 0 ...
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Table 3. A29800 Bottom Boot Block Sector Address Table Sector A18 A17 A16 A15 SA0 SA1 SA2 SA3 SA4 SA5 ...
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Table 4. A29800 Autoselect Codes (High Voltage Method) CE Description Mode Manufacturer ID: AMIC L Device ID: A29800 Word L (Top Boot Block) Byte Device ID: A29800 Word L (Bottom Boot Byte Block) Continuation ID L Sector Protection L Verification ...
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Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection must be implemented using programming equipment. The ...
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Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence ...
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START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data ? Increment Address Last Address ? Programming Completed Note : See the appropriate Command Definitions table for program command sequence. Figure 2. Program Operation ...
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Figure 3 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms. Erase Suspend/Erase Resume Commands The Erase Suspend ...
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Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ID 4 Byte Word Device ID, 4 Byte Top Boot Block Word Device ID, 4 Bottom Boot Block Byte Word Continuation ID 4 Byte Word Sector ...
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Write Operation Status Several bits, I/O , I/O , I provided in the A29800 to determine the status of a write operation. Table 6 and the following subsections describe the functions of these status bits. ...
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BY : Read/ Busy RY/ The RY dedicated, open-drain output pin that indicates whether an Embedded algorithm is in progress or complete. The RY/ BY status is valid after the rising edge of the final WE pulse ...
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I/O : Exceeded Timing Limits 5 I/O indicates whether the program or erase time has 5 exceeded a specified internal pulse count limit. Under these conditions I/O produces a "1." This is a failure 5 condition that indicates the program ...
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Operation Standard Embedded Program Algorithm Mode Embedded Erase Algorithm Erase Reading within Erase Suspend Suspended Sector Mode Reading within Non-Erase Suspend Sector Erase-Suspend-Program Notes: 1. I/O and I/O require a valid address when reading status information. Refer to the appropriate ...
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DC Characteristics TTL/NMOS Compatible Parameter Parameter Description Symbol I Input Load Current LI I A9, OE & RESET Input Load Current LIT I Output Leakage Current LO I VCC Active Read Current CC1 (Notes 1, 2) VCC Active Write (Program/Erase) ...
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AC Characteristics Read Only Operations Parameter Symbols JEDEC Std t t Read Cycle Time (Note 2) AVAV Address to Output Delay AVQV ACC t Chip Enable to Output Delay t ELQV CE Output Enable to Output Delay ...
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AC Characteristics Hardware Reset ( RESET ) Parameter JEDEC Std RESET Pin Low (During Embedded t READY Algorithms) to Read or Write (See Note) RESET Pin Low (Not During Embedded t READY Algorithms) to Read or Write (See Note) t ...
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Temporary Sector Unprotect Parameter JEDEC Std t V Rise and Fall Time (See Note) VIDR ID RESET Setup Time for Temporary Sector t RSP Unprotect Note: Not 100% tested. Temporary Sector Unprotect Timing Diagram 12V RESET t ...
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AC Characteristics BYTE Word/Byte Configuration ( ) Parameter JEDEC Std t t ELFL/ ELFH BYTE FLQZ BYTE Switching Low to Output High-Z t FHQV BYTE Switching High to Output Active BYTE Timings for Read Operations CE OE ...
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AC Characteristics Erase and Program Operations Parameter JEDEC Std t Write Cycle Time (Note 1) t AVAV WC Address Setup Time t t AVWL Address Hold Time WLAX Data Setup Time DVWH DS Data ...
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Timing Waveforms for Program Operation Program Command Sequence (last two cycles Addresses 555h CE t GHWL Data RY/BY t VCS VCC Note : program addrss program data, Dout is ...
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Timing Waveforms for Chip/Sector Erase Operation Erase Command Sequence (last two cycles Addresses 2AAh CE t GHWL Data RY/BY t VCS VCC Note : Sector Address (for Sector Erase ...
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Timing Waveforms for Data Polling (During Embedded Algorithms Addresses VA t ACC OEH WE I/O 7 I BUSY RY/BY Note : VA = Valid Address. Illustation ...
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Timing Waveforms for Toggle Bit (During Embedded Algorithms Addresses VA t ACC OEH WE I BUSY RY/BY Note Valid Address; not required for I/O ...
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Timing Waveforms for I/O vs. I/O 2 Enter Erase Embedded Suspend Erasing WE Erase Erase Suspend I/O 6 I/O 2 I/O and I/O toggle with OE and Note : Both I/O and I/O toggle with OE or ...
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Timing Waveforms for Alternate CE Controlled Write Operation ( RESET 555 for program 2AA for erase Addresses GHEL Data for program 55 for erase RESET RY/BY Note ...
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Latch-up Characteristics Input Voltage with respect to VSS on all I/O pins VCC Current Input voltage with respect to VSS on all pins except I/O pins (including A9, OE and RESET ) Includes all pins except VCC. Test conditions: VCC ...
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Test Conditions Test Specifications Test Condition Output Load Output Load Capacitance, C (including jig capacitance) L Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Test Setup Device Under Test PRELIMINARY ...
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... Ordering Information Top Boot Sector Flash Access Time Part No. (ns) A29800TM-55 55 A29800TV-55 A29800TM-70 70 A29800TV-70 A29800TM-90 90 A29800TV-90 Bottom Boot Sector Flash Access Time Part No. (ns) A29800UM-55 55 A29800UV-55 A29800UM-70 70 A29800UV-70 A29800UM-90 90 A29800UV-90 PRELIMINARY (May, 2001, Version 0.0) Active Read Program/Erase Current Current Typ. (mA) Typ ...
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Package Information SOP 44L Outline Dimensions Seating Plane Symbol Notes: 1. The maximum value of dimension D includes ...
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Package Information TSOP 48L (Type I) Outline Dimensions 1 24 Detail "A" Symbol Notes: 1. The maximum value of dimension D includes end flash. 2. ...