A29800TM-55 AMICC [AMIC Technology], A29800TM-55 Datasheet - Page 15
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A29800TM-55
Manufacturer Part Number
A29800TM-55
Description
1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory
Manufacturer
AMICC [AMIC Technology]
Datasheet
1.A29800TM-55.pdf
(34 pages)
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RY/
The RY/
indicates whether an Embedded algorithm is in progress
or complete. The RY/
edge of the final
Since RY/
pins can be tied together in parallel with a pull-up resistor
to VCC.
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase
Suspend mode), or is in the standby mode.
Table 6 shows the outputs for RY/
Timings”, “Timing Waveforms for Program Operation” and
“Timing Waveforms for Chip/Sector Erase Operation” for
more information.
I/O
Toggle Bit I on I/O
Program or Erase algorithm is in progress or complete, or
whether the device has entered the Erase Suspend mode.
Toggle Bit I may be read at any address, and is valid after
the rising edge of the final
sequence (prior to the program or erase operation), and
during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address cause
I/O
control the read cycles.) When the operation is complete,
I/O
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O
approximately 100 s, then returns to reading array data. If
not all selected sectors are protected, the Embedded
Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected.
The system can use I/O
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), I/O
device enters the Erase Suspend mode, I/O
toggling. However, the system must also use I/O
determine which sectors are erasing or erase-suspended.
Alternatively, the system can use I/O
on " I/O
If a program address falls within a protected sector, I/O
toggles for approximately 2 s after the program command
sequence is written, then returns to reading array data.
I/O
mode, and stops toggling once the Embedded Program
algorithm is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on I/O
algorithm, and to the Toggle Bit Timings figure in the "AC
Characteristics" section for the timing diagram. The I/O
vs. I/O
PRELIMINARY
6
6
6
6
BY : Read/ Busy
: Toggle Bit I
stops toggling.
to toggle. (The system may use either
also toggles during the erase-suspend-program
6
7
figure shows the differences between I/O
:
BY
Data
BY
is a dedicated, open-drain output pin that
is an open-drain output, several RY/
Polling").
WE
(May, 2001, Version 0.0)
6
. Refer to Figure 5 for the toggle bit
6
BY
pulse in the command sequence.
indicates whether an Embedded
6
and I/O
status is valid after the rising
WE
2
pulse in the command
BY
together to determine
7
6
. Refer to “
(see the subsection
toggles. When the
6
OE
toggles for
2
or
RESET
and I/O
6
CE
stops
2
BY
to
to
6
2
6
15
in graphical form. See also the subsection on " I/O
Toggle Bit II".
I/O
The "Toggle Bit II" on I/O
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final
sequence.
I/O
those sectors that have been selected for erasure. (The
system may use either
cycles.) But I/O
actively
comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both status
bits are required for sector and mode information. Refer to
Table 6 to compare outputs for I/O
Figure 5 shows the toggle bit algorithm in flowchart form,
and the section " I/O
See also the " I/O
Toggle Bit Timings figure for the toggle bit timing diagram.
The I/O
and I/O
Reading Toggle Bits I/O
Refer to Figure 5 for the following discussion. Whenever
the system initially begins reading toggle bit status, it must
read I/O
whether a toggle bit is toggling. Typically, a system would
note and store the value of the toggle bit after the first
read. After the second read, the system would compare
the new value of the toggle bit with the first. If the toggle
bit is not toggling, the device has completed the program
or erase operation. The system can read array data on
I/O
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of I/O
section on I/O
again whether the toggle bit is toggling, since the toggle bit
may have stopped toggling just as I/O
toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still
toggling, the device did not complete the operation
successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and I/O
gone high. The system may continue to monitor the toggle
bit and I/O
the status as described in the previous paragraph.
Alternatively, it may choose to perform other system tasks.
In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the
operation (top of Figure 5).
2
7
2
: Toggle Bit II
- I/O
toggles when the system reads at addresses within
2
6
vs. I/O
in graphical form.
7
0
erasing
on the following read cycle.
- I/O
5
through successive read cycles, determining
5
). If it is, the system should then determine
6
2
0
figure shows the differences between I/O
cannot distinguish whether the sector is
6
at least twice in a row to determine
: Toggle Bit I" subsection. Refer to the
or
2
: Toggle Bit II" explains the algorithm.
is
2
OE
, when used with I/O
AMIC Technology, Inc.
WE
6
erase-suspended.
, I/O
or
pulse in the command
CE
2
2
and I/O
A29800 Series
to control the read
5
5
went high. If the
is high (see the
6
.
6
, indicates
I/O
5
has not
6
,
by
2
2
: