LM95172QA2MDA NSC [National Semiconductor], LM95172QA2MDA Datasheet - Page 12

• Manufacturer Part Number: LM95172QA2MDA
• Manufacturer: NSC [National Semiconductor]

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1.4 COMMUNICATING WITH THE LM95172Q
The serial interface consists of three lines: CS (Chip Select),
SC (Serial Clock), and the bi-directional SI/O (Serial I/O) data
line. See (Note 7)for CS voltage restriction. A high-to-low
transition of the CS line initiates the communication. The
master (processor) always drives the chip select and the
clock. The first 16 clocks shift the temperature data out of the
LM95172Q on the SI/O line (a temperature read). Raising the
CS at anytime during the communication will terminate this
read operation. Following this temperature read, the SI/O line
becomes an input and a command byte can be written to the
FIGURE 11. Reading the Temperature Register followed by a read or write from another register (Control/Status, T
FIGURE 12. Reading the Temperature Register followed by repeated commands and Data Register accesses (Control/
FIGURE 10. Reading the Temperature Register
Status, T
T
LOW
HIGH
, or Identification register)
, T
LOW
, or Identification register)
12
LM95172Q. This command byte contains a R/W bit and the
address of the register to be communicated with next (see
Section 1.7 Internal Register Structure). When writing, the
data is latched in after every 8 bits. The processor must write
at least 8 bits in order to latch the data. If CS is raised before
the falling edge of the 8th command bit, no data will be latched
into the command byte. If CS is raised after the 8th data-reg-
ister write bit, but before the 16th bit, only the most significant
byte of the data will be latched. This command-data-com-
mand-data sequence may be performed as many times as
desired.
30035714
30035716
30035715
HIGH
,