EMC12 ETC2 [List of Unclassifed Manufacturers], EMC12 Datasheet - Page 11

• Manufacturer Part Number: EMC12
• Description: Audio Interface for the EmPack System
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

09 Jan 2006
Bit(s)
0
1
2
3
4
5 - 10
11 - 14
15
PIO_A[1-5]
0x00
0x01 - 0x1F
PIO_A[1-5]
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0a
0x0b
0x0c
0x0d
0x0e - 0x1F
Bit(s)
0
1
2
Name
DSP_RESET
DSP_MMODE
TDM_RESET
Reserved
ACTIVE_FIFO
CODEC_RESET
Reserved
DIGI_LOOP
Table 1-5: Register Map For SYSTEM Resource
Table 1-6: Board Control Register 0 (BCR0)
Table 1-7: Board Control Register 1 (BCR1)
Name
AV9110_EN
DS1620_EN
FIFO_RESET
Access
Read/Write
Access
Read/Write
Read/Write
Read
Read/Write
Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Communication Automation Corporation
EMC12 Hardware Reference Manual
Access
Read/Write
Read/Write
Read/Write
Read Only
Read/Write
Read/Write
Register
TDM Control Data Register (TCDR)
Reserved
Access
Read/Write
Read/Write
Write Only
Register
Board Control Register 0 (BCR0)
Board Control Register 1 (BCR1)
PIO Interrupt Status (PISR)
PIO Interrupt Mask (PIMR)
DSP Interrupt Control (DICR)
Last TDM Control Word (LTCW)
CODEC test points select (bits 0 – 2)
Test point diagnostic signal (bit 0)
CODEC 0 Control Status (CCS0)
CODEC 1 Control Status (CCS1)
CODEC 2 Control Status (CCS2)
CODEC 3 Control Status (CCS3)
CODEC 4 Control Status (CCS4)
CODEC 5 Control Status (CCS5)
Reserved
Function
Control RESTN (active low) pin of each DSP
DSP memory mode:
0 = mode 6
1 = mode 7
TDM reset
Currently active FIFO
Assert Power-Down to Codecs 0 - 5
Experimental Digital Loop-back mode
Function
AV9110 Chip Select:
0 = chip deselected
1 = chip selected
0 = chip deselected
1 = chip selected
Reset inactive FIFO
Location
FIFO
Device
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
FPGA
1-7