EMC12 ETC2 [List of Unclassifed Manufacturers], EMC12 Datasheet - Page 15

• Manufacturer Part Number: EMC12
• Description: Audio Interface for the EmPack System
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

EMC12 Hardware Reference Manual
1.2.3 Reset and Configuration
The EEPROM (NM93C46M8) contains board specific information for the mezzanine. The TCK and
TDO signals are connected to the SK and DO pins of the EEPROM. MODID0 and MODID3 are
AND’ed together and connected to the DI pin. The base board can use the information stored in the
EEPROM to configure the EMC12 appropriately.
Note that the sequence of numbers used for MODID is {0x7, 0x3, 0x1, 0x0, 0x8, 0xC, 0xE, 0xF}. 0xF is
the only number whose MODID0 and MODID3 bits AND’ed together gives ‘1’. This means to shift a
‘1’ into the DI pin of the EEPROM, the base board needs to drive a value to MODID such that the
targeted mezzanine sees 0xF as the MODID. Any other value will present a ‘0’ at the DI pin. For
example, if the base board wants to interrogate the EEPROM of the second mezzanine, it needs to send a
sequence of ‘1’s and ‘0’s to the EEPROM. To send a ‘1’, it should drive 0xE to MODID, and to send a
‘0’, it can drive 0x7.
Activating the PROGRAM- signal clears the FPGA (XC4013E) internal configuration memory and the
FPGA is ready for reprogramming. The TDI, TDO, TCK signals are connected to the respective pins on
the FPGA. The MODID0 and MODID3 signals are NAND’ed and connected to the TMS pin of the
FPGA. These four pins are used to program the device with the JTAG Configure command. Note the
INIT- pin of the FPGA is pulled low to prevent the device from entering normal configuration through the
Mode pins.
Since the signals are shared between the FPGA and EEPROM, EECS is used to select the intended
device. When EECS is active, the EEPROM is enabled. The EECS signal is also OR’ed with TMS so
that when EECS is a ‘1’ the TMS input of the FPGA is also a ‘1’. This keeps the JTAG in the idle state
when the EEPROM is being accessed.
The RESET- signal is connected to the FPGA Global Set/Reset net, and the ZN pin of each DSP. When
RESET- is active (low), all DSP outputs are tri-stated and the FPGA internal registers are put in a known
state. The DSP_RESET bit in BCR0 becomes ‘0’ which halts all the DSPs on the mezzanine. In
addition, the FIFOs are reset and all TDM control information is cleared.
09 Jan 2006
Communication Automation Corporation
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