LM96163C NSC [National Semiconductor], LM96163C Datasheet - Page 6

• Manufacturer Part Number: LM96163C
• Manufacturer: NSC [National Semiconductor]

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f
t
t
t
t
t
t
t
t
t
t
t
t
SMB
LOW
HIGH
R
F
OF
TIMEOUT
SU:DAT
HD:DAT
HD:STA
SU:STO
SU:STA
BUF
Symbol
SMBus Digital Switching Characteristics
Unless otherwise noted, these specifications apply for V
pF. Boldface limits apply for T
characteristics of the LM96163 fully meet or exceed the published specifications of the SMBus version 2.0. The following param-
eters are the timing relationships between SMBCLK and SMBDAT signals related to the LM96163. They adhere to but are not
necessarily the same as the SMBus bus specifications.
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise noted.
Note 3: When the input voltage (V
components and/or ESD protection circuitry are shown below for the LM96163's pins. Care should be taken not to forward bias the parasitic diode, D2, present
on pins D+ and D−. Doing so by more than 50 mV may corrupt temperature measurements.
SMBus Clock Frequency
SMBus Clock Low Time
SMBus Clock High Time
SMBus Rise Time
SMBus Fall Time
Output Fall Time
SMBDAT and SMBCLK Time Low for Reset of
Serial Interface See (Note 14)
Data In Setup Time to SMBCLK High
Data Out Hold Time after SMBCLK Low
Hold Time after (Repeated) Start Condition. After
this period the first clock is generated.
Stop Condition SMBCLK High to SMBDAT Low
(Stop Condition Setup)
SMBus Repeated Start-Condition Setup Time,
SMBCLK High to SMBDAT Low
SMBus Free Time between Stop and Start
Conditions
IN
Parameter
) at any pin exceeds the power supplies (V
A
SMBus Timing Diagram for SMBCLK and SMBDAT Signals
= T
J
; T
MIN
≤
T
A
≤
T
MAX
DD
; all other limits T
= +3.0 VDC to +3.6 VDC, C
From V
From V
(Note 12)
(Note 13)
C
L
= 400 pF, I
IN
6
< GND or V
IN(0) max
IN(1) min
A
O
IN
to V
to V
= T
= 3 mA
> V+), the current at that pin should be limited to 5 mA. Parasitic
Conditions
IN(1) min
J
IN(0) max
= +25°C, unless otherwise noted. The switching
L
(load capacitance) on output lines = 80
(Note 9)
Limits
1075
100
250
250
300
100
4.7
4.0
0.3
4.0
4.7
4.7
10
50
25
35
1
30041004
kHz (max)
kHz (min)
ms (max)
µs (max)
µs (max)
µs (max)
ns (max)
ms (min)
ns (max)
µs (min)
µs (min)
ns (min)
ns (min)
µs (min)
ns (min)
µs (min)
µs (min)
(Limit)
Units