IP200 ETC [List of Unclassifed Manufacturers], IP200 Datasheet - Page 21

• Manufacturer Part Number: IP200
• Description: Interpolation Circuit for Incremental Measuring Systems
• Manufacturer: ETC [List of Unclassifed Manufacturers]

8
The IP200 has 6 sources for generating the global error signal. Each source can be activated by the
corresponding bit in the error mask register. With the LatchErr bit being activated, the individual error
signals are stored until the next chip reset or until the next SPI ResetCount command (command 0x01)
occurs, respectively. The logic OR function of the masked and stored error signals appears as a low active
signal on pin NERR. With the HoldErr bit being active, the A, B and OREF outputs freeze in the current state
on error case. The NERR and NRES pins can be shorted in order to re-synchronise the IC in the event of an
error. The error signal is active for 8 system clocks in this case.
Error Mask Register

For square wave operation (A/B-Signals) it is recommended to set the error mask register to 0x3F or 0xFF
respectively, in counter mode use the error mask register loaded with 0xDF and set the SPEED bit in the
CFG0 register.
The status register STAT contains all error bits. The MVAL and CNT register contain logic combinations
of counter relevant error bits:
Sensor breakage error:
Partial or complete tearing off of the connected sensor is detected in the IP200 at the time of occurrence.
Thereafter, the automatic gain-offset-controller tries to compensate this error which, due to the large
operating range of the gain-offset-controller, can lead to a situation where the cause of this error seems to
have been eliminated.
Bit
GCOMP
OCOMP
BQLOW
ADUOVL
FAST1
FAST2
HoldErr
LatchErr
D-09116 Chemnitz, Germany
Error Processing
Zwickauer Straße 227
SENSERR = ADUOVL or BQLOW or OCOMP or GCOMP
AMPERR = ADUOVL or BQLOW
GEMAC
Gesellschaft für
Mikroe lektronikanwendung Chemnitz mbH
Description (if bit is set)
Gain controller reaches his limit
Offset controller reaches his limit
Amplitude Error: the resulting Sine-Cosine-Vector is to small
One or both ADC-Converter are clipping
Signal frequency to high, no signal direction recognition possible (SPEED=1),
Signal frequency to fast for proper generating A/B/OREF - Signals (SPEED=0)
Signal frequency to fast for proper generating the A/B/OREF - Signals (depends
upon IT(2:0), refer also to table “Clock Frequency Examples” in chapter 4.4)
The A/B/OREF - Signals freeze in error case
The masked error signal is stored until next SPI-reset-command or a global reset
occurs, respectively
Phone:
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Date: 20.04.04
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Page 21 of 30
Title:
Data Sheet GC-IP200
Name of Document:
43500-DB-2-1-E-IP200.pdf