IP200 ETC [List of Unclassifed Manufacturers], IP200 Datasheet - Page 9

• Manufacturer Part Number: IP200
• Description: Interpolation Circuit for Incremental Measuring Systems
• Manufacturer: ETC [List of Unclassifed Manufacturers]

4.2
An error signal is generated if the input signals are no longer plausible. The error signal is also generated if
the input frequency is so high that the square-wave signals are unable to follow, and/or when the maximum
input frequency is exceeded. The evaluation of the internal error sources is activated via an error mask
register. The response of the square-wave outputs in the event of an error can also be configured via this
register. The NERR and NRES pins can be connected in order to start a re-synchronisation process of the IC
in the event of an error.

If the error signal was activated, and/or if one of the error bits was set in the result register, the present
measuring result and all the following results must be discarded. Following elimination of the cause of the
error and a reset of the error bit, the reference point must once again be passed by for absolute value
measurements!
4.3
The interpolation rate can be set at 200, 160, 100, 80, 50, 40, 25 and 20. The interpolation rate as defined
for the purposes of this application is the number of increments into which one sine period of the input signal
is divided. This also corresponds to the number of edge changes on the A/B output signals per input signal
period. This means that the number of square-wave periods at the A and B outputs totals 1/4 of the
interpolation rate per input signal period.

In the event that a standard interpolation counter or quadrature decoder is connected to the A/B outputs, this
must work in "quadruple evaluation" mode in order to achieve the full interpolation rate.
4.4
The interval time (IT) and the minimum edge distance t
binary steps at values between 1/f
In counter mode (the SPEED Bit in the CFG0 Register being set), the maximum input frequency totals
f
distance at the output, where:
The limit values are a maximum input frequency of aprox. 400kHz with a clock frequency of 40MHz on the
one hand, as well as a guaranteed edge distance of 128µs at the A/B signals with a clock frequency of 1MHz
on the other. Between these two limits, a large number of specific systems can be adapted by selecting a
suitable clock frequency and interval time of the IP200.

These values apply on condition of an adjusted phase between the input signals and a steady state of the
internal gain-offset-controller. Until this time, the input frequency must not exceed 50% of the specified
maximum frequency.
max
D-09116 Chemnitz, Germany
=f
Zwickauer Straße 227
Error Signal
Interpolation Rate
Interval Time / Maximum Input Frequency
osc
f
f
IR:
IT:
GEMAC
Gesellschaft für
Mikroe lektronikanwendung Chemnitz mbH
max
osc
/96. In all the other modes, the maximum input frequency is limited by the minimum pulse
:
 0.9*f
Clock frequency at Pin XA
Activated Interpolation Rate
Activated Interval Time
OSZ
/(IRIT) <
Phone:
Fax::
Internet:
Email:
Date: 20.04.04
osz
and 128/f
[phone] - 0
[phone]
www.gemac-chemnitz.de
[e-mail]
[e-mail]
f
osz
/96
osz
.
Page 9 of 30
pp
at the output signals, respectively, can be set in
Title:
Data Sheet GC-IP200
Name of Document:
43500-DB-2-1-E-IP200.pdf