PXF4333V11 INFINEON [Infineon Technologies AG], PXF4333V11 Datasheet - Page 306

• Manufacturer Part Number: PXF4333V11
• Description: ABM 3G ATM Buf fer Manager
• Manufacturer: INFINEON [Infineon Technologies AG]

Register 106 IMRC
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
IMRC(15:0)
Data Sheet
15
7
Interrupt Mask Register Common
14
Interrupt Mask Common
Each bit controls whether the corresponding interrupt indication in
register ISRC (same bit location) activates the interrupt signal:
1
0
6
Read/Write
0000
IMRC
Written by CPU to control interrupt signal effective
events
H
13
5
Interrupt indication masked.
The interrupt signal is not activated upon this event.
Interrupt indication unmasked.
The interrupt signal is activated upon this event.
E8
H
12
IMRC(15:8)
4
IMRC(7:0)
306
11
3
10
2
Register Description
PXF 4333 V1.1
9
1
2001-12-17
ABM-3G
8
0