AT90PWM2B-16SE ATMEL [ATMEL Corporation], AT90PWM2B-16SE Datasheet - Page 36

• Manufacturer Part Number: AT90PWM2B-16SE
• Description: 8-bit Microcontroller with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

7.6.2
7.7
7.8
36
128 kHz Internal Oscillator
External Clock
AT90PWM2/3/2B/3B
PLL Control and Status Register – PLLCSR
Figure 7-5.
• Bit 7..3 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM2/2B/3/3B and always read as zero.
• Bit 2 – PLLF: PLL Factor
The PLLF bit is used to select the division factor of the PLL.
If PLLF is set, the PLL output is 64Mhz.
If PLLF is clear, the PLL output is 32Mhz.
• Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is
started as PLL reference clock. If PLL is selected as a system clock source the value for this bit
is always 1.
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable
CLK
The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-
quency is nominal at 3V and 25°C. This clock is used by the Watchdog Oscillator.
To drive the device from an external clock source, XTAL1 should be driven as shown in
7-6. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
Bit
$29 ($29)
Read/Write
Initial Value
PLL
XTAL1
XTAL2
for PSC. After the PLL is enabled, it takes about 100 ms for the PLL to lock.
RC OSCILLATOR
OSCCAL
8 MHz
PCK Clocking System AT90PWM2B/3B
OSCILLATORS
R
7
–
0
R
6
–
0
CKSEL3..0
R
5
–
0
DIVIDE
BY 8
R
4
–
0
PLLE
PLL
64x
R
3
–
0
Detector
Lock
DIVIDE
DIVIDE
PLLF
PLLF
BY 2
BY 4
R/W
2
0
PLLE
R/W
0/1
1
PLOCK
CLK
PLOCK
R
0
0
CK
PLL
SOURCE
4317J–AVR–08/10
PLLCSR
Figure