PIC24HJ32GP202 MICROCHIP [Microchip Technology], PIC24HJ32GP202 Datasheet - Page 153
![no-image](/images/no-image-200.jpg)
PIC24HJ32GP202
Manufacturer Part Number
PIC24HJ32GP202
Description
High-Performance, 16-bit Microcontrollers
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC24HJ32GP202.pdf
(244 pages)
- Current page: 153 of 244
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16.0
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules avail-
able
PIC24HJ16GP304 device family. The UART is a full-
duplex asynchronous system that can communicate
with peripheral devices, such as personal computers,
LIN, RS-232 and RS-485 interfaces. The module also
supports a hardware flow control option with the
UxCTS and UxRTS pins and also includes an IrDA
encoder and decoder.
The primary features of the UART module are:
• Full-Duplex 8- or 9-bit Data Transmission through
• Even, odd or no parity options (for 8-bit data)
• One or two stop bits
• Hardware Flow Control Option with UxCTS and
FIGURE 16-1:
© 2007 Microchip Technology Inc.
Note:
the UxTX and UxRX pins
UxRTS pins
in
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
This data sheet summarizes the features
of
PIC24HJ16GP304 devices. It is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to the “PIC24H
Family Reference Manual”.
PIC24HJ32GP202/204 and PIC24HJ16GP304
the
the
UART SIMPLIFIED BLOCK DIAGRAM
PIC24HJ32GP202/204
PIC24HJ32GP202/204
Hardware Flow Control
Baud Rate Generator
UART Transmitter
UART Receiver
IrDA
®
and
and
Preliminary
®
• Fully Integrated Baud Rate Generator with 16-bit
• Baud rates ranging from 1 Mbps to 15 Mbps at
• 4-deep first-in-first-out (FIFO) Transmit Data
• 4-Deep FIFO Receive Data Buffer
• Parity, framing and buffer overrun error detection
• Support for 9-bit mode with Address Detect
• Transmit and Receive interrupts
• A separate interrupt for all UART error conditions
• Loopback mode for diagnostic support
• Support for Sync and Break characters
• Support for automatic baud rate detection
• IrDA encoder and decoder logic
• 16x baud clock output for IrDA support
A simplified block diagram of the UART module is
shown in Figure 16-1. The UART module consists of
the following key hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
prescaler
16 MIPS
Buffer
(9th bit = 1)
BCLK
UxRTS
UxCTS
UxRX
UxTX
DS70289A-page 151
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