PIC24HJ32GP202 MICROCHIP [Microchip Technology], PIC24HJ32GP202 Datasheet - Page 45
![no-image](/images/no-image-200.jpg)
PIC24HJ32GP202
Manufacturer Part Number
PIC24HJ32GP202
Description
High-Performance, 16-bit Microcontrollers
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC24HJ32GP202.pdf
(244 pages)
- Current page: 45 of 244
- Download datasheet (4Mb)
REGISTER 4-1:
© 2007 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-4
bit 3-0
Note 1:
R/SO-0
WR
U-0
—
2:
(1)
These bits can only be reset on POR.
All other combinations of NVMOP<3:0> are unimplemented.
PIC24HJ32GP202/204 and PIC24HJ16GP304
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
0 = Program or erase operation is complete and inactive
WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
0 = The program or erase operation completed normally
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit
1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command
0 = Perform the program operation specified by NVMOP<3:0> on the next WR command
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits
If ERASE = 1:
1111 = Memory bulk erase operation
1101 = Erase General Segment
1100 = Erase Secure Segment
0011 = No operation
0010 = Memory page erase operation
0001 = No operation
0000 = Erase a single Configuration register byte
If ERASE = 0:
1111 = No operation
1101 = No operation
1100 = No operation
0011 = Memory word program operation
0010 = No operation
0001 = Memory row program operation
0000 = Program a single Configuration register byte
R/W-0
R/W-0
ERASE
WREN
cleared by hardware once operation is complete.
automatically on any set attempt of the WR bit)
NVMCON: FLASH MEMORY CONTROL REGISTER
(1)
(1)
SO = Satiable only bit
W = Writable bit
‘1’ = Bit is set
R/W-0
WRERR
U-0
—
(1)
U-0
U-0
Preliminary
—
—
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
—
(1)
R/W-0
U-0
—
NVMOP<3:0>
(1)
x = Bit is unknown
R/W-0
U-0
(2)
—
(1)
DS70289A-page 43
R/W-0
U-0
—
(1)
bit 8
bit 0
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