ATMEGA48V_06 ATMEL [ATMEL Corporation], ATMEGA48V_06 Datasheet - Page 309

• Manufacturer Part Number: ATMEGA48V_06
• Description: 8-bit Microcontroller with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

27.7
2545J–AVR–12/06
3. C
4. f
5. This requirement applies to all ATmega48/88/168 2-wire Serial Interface operation. Other devices connected to the 2-wire
6. The actual low period generated by the ATmega48/88/168 2-wire Serial Interface is (1/f
7. The actual low period generated by the ATmega48/88/168 2-wire Serial Interface is (1/f
SPI Timing Characteristics
Serial Bus need only obey the general f
than 6 MHz for the low time requirement to be strictly met at f
ment will not be strictly met for f
communicate at full speed (400 kHz) with other ATmega48/88/168 devices, as well as any other device with a proper t
acceptance margin.
CK
b
= capacitance of one bus line in pF.
= CPU clock frequency
Figure 27-4. 2-wire Serial Bus Timing
See
Table 27-6.
Note:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Figure 27-5
SCL
SDA
Description
SCK period
SCK high/low
Rise/Fall time
Setup
Hold
Out to SCK
SCK to out
SCK to out high
SS low to out
SCK period
SCK high/low
Rise/Fall time
Setup
Hold
SCK to out
SCK to SS high
SS high to tri-state
SS low to SCK
1. In SPI Programming mode the minimum SCK high/low period is:
t
SU;STA
- 2 t
- 3 t
SCL
SPI Timing Parameters
CLCL
CLCL
> 308 kHz when f
and
for f
for f
(1)
SCL
Figure 27-6
CK
CK
requirement.
< 12 MHz
> 12 MHz
t
HD;STA
t
t
of
LOW
Mode
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
CK
for details.
= 8 MHz. Still, ATmega48/88/168 devices connected to the bus may
t
HIGH
SCL
t
HD;DAT
Min
4 • t
2 • t
10
t
20
20
ck
= 100 kHz.
ck
ck
t
LOW
t
SU;DAT
Typ
See
50% duty cycle
3.6
10
10
0.5 • t
10
10
15
15
10
ATmega48/88/168
Table 17-5
SCL
SCL
sck
- 2/f
- 2/f
CK
CK
), thus the low time require-
), thus f
t
SU;STO
Max
1600
t
CK
r
must be greater
t
BUF
LOW
309
ns