ATMEGA48V_06 ATMEL [ATMEL Corporation], ATMEGA48V_06 Datasheet - Page 39

• Manufacturer Part Number: ATMEGA48V_06
• Description: 8-bit Microcontroller with 8K Bytes In-System Programmable Flash
• Manufacturer: ATMEL [ATMEL Corporation]

8. Power Management and Sleep Modes
8.1
8.2
2545J–AVR–12/06
Sleep Modes
Idle Mode
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
Figure 7-1 on page 27
distribution. The figure is helpful in selecting an appropriate sleep mode.
different sleep modes and their wake up sources.
Table 8-1.
Notes:
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select
which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be
activated by the SLEEP instruction. See
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial
Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep
mode basically halts clk
Sleep Mode
Idle
ADC Noise
Reduction
Power-down
Power-save
Standby
1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT1 and INT0, only level interrupt.
(1)
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains
presents the different clock systems in the ATmega48/88/168, and their
CPU
X
and clk
X
X
FLASH
X
X
X
, while allowing the other clocks to run.
Table 8-2 on page 43
Oscillators
X
X
X
X
X
X
(2)
(2)
(2)
X
X
X
X
X
(3)
(3)
(3)
(3)
ATmega48/88/168
for a summary.
X
X
X
X
X
Wake-up Sources
X
X
X
(2)
Table 8-1
X
X
X
X
shows the
X
X
X
X
X
X
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