AT32UC3A0512-ALTES ATMEL [ATMEL Corporation], AT32UC3A0512-ALTES Datasheet - Page 77

• Manufacturer Part Number: AT32UC3A0512-ALTES
• Description: AVR32 32-Bit Microcontroller
• Manufacturer: ATMEL [ATMEL Corporation]

15.4.6
15.4.7
32058FS–AVR32–08/08
SDRAMC
USART
12. CPU cannot operate on a divided slow clock (internal RC oscillator)
1.
2.
1.
2.
3.
4.
5. USART SPI mode is non functional on this revision.
6. DCD is active High instead of Low.
Fix/Workaround
Do not run the CPU on a divided slow clock.
Code execution from SDRAM does not work.
Fix/Workaround
Do not run code from SDRAM.
SDCKE rise at the same time as SDCK while exiting self-refresh mode.
Fix/Workaround
None.
Manchester encoding/decoding is not working.
Fix/Workaround
Do not use manchester encoding.
In asynchronous mode the RXBREAK flag is not correctly handled when the timeguard is 0
and the break character is located just after the stop bit.
Fix/Workaround
If the NBSTOP is 1, timeguard should be different from 0.
If CTS switches from 0 to 1 during the TX of a character, if the Holding register is not empty,
the TXHOLDING is also transmitted.
Fix/Workaround
None.
Manchester encoding/decoding is not working.
Fix/Workaround
Do not use manchester encoding.
Fix/Workaround
Do not use the USART SPI mode.
In modem mode the DCD signal is assumed to be active high by the USART, butshould
have been active low.
Fix/Workaround
Code execution from external SDRAM does not work
SDRAM SDCKE rise at the same time as SDCK while exiting self-refresh mode
USART Manchester Encoder Not Working
USART RXBREAK problem when no timeguard
USART Handshaking: 2 characters sent / CTS rises when TX
USART PDC and TIMEGUARD not supported in MANCHESTER
AT32UC3A
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