AT32UC3A0512-ALTES ATMEL [ATMEL Corporation], AT32UC3A0512-ALTES Datasheet - Page 80
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AT32UC3A0512-ALTES
Manufacturer Part Number
AT32UC3A0512-ALTES
Description
AVR32 32-Bit Microcontroller
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT32UC3A0512-ALTES.pdf
(86 pages)
- Current page: 80 of 86
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15.4.13
15.4.14
15.4.15
15.4.16
15.4.17
32058FS–AVR32–08/08
RTC
OCD
PDCA
TWI
Processor and Architecture
1. Writes to control (CTRL), top (TOP) and value (VAL) in the RTC are discarded if the
2. The RTC CLKEN bit (bit number 16) of CTRL register is not available.
1. Stalled memory access instruction writeback fails if followed by a HW breakpoint.
1. Wrong PDCA behavior when using two PDCA channels with the same PID.
1. The TWI RXRDY flag in SR register is not reset when a software reset is performed.
1. LDM instruction with PC in the register list and without ++ increments Rp
- After a FLASHC Write Page (WP) or Erase Page (EP) command applied to a page in a
given half of the flash (first or last 256 kB of flash), reading (data read or code fetch) the
other half of the flash may fail. This may lead to an exception or to other errors derived from
this corrupted read access.
- After a FLASHC Erase All (EA) command, reading (data read or code fetch) the flash may
fail. This may lead to an exception or to other errors derived from this corrupted read access.
- After a FLASHC Write User Page (WUP) or Erase User Page (EUP) command, reading
(data read or code fetch) the second half (last 256 kB) of the flash may fail. This may lead to
an exception or to other errors derived from this corrupted read access.
Fix/Workaround
Flashc WP, EP, EA, WUP, EUP commands: these commands must be issued from RAM or
through the EBI. After these commands, read twice one flash page initialized to 00h in each
half part of the flash.
RTC peripheral bus clock (PBA) is divided by a factor of four or more relative to the
HSB clock.
Fix/Workaround
Do not write to the RTC registers using the peripheral bus clock (PBA) divided by a factor of
four or more relative to the HSB clock.
Fix/Workaround
Do not use the CLKEN bit of the RTC on Rev E.
Consider the following assembly code sequence:
A
B
If a hardware breakpoint is placed on instruction B, and instruction A is a memory access
instruction, register file updates from instruction A can be discarded.
Fix/Workaround
Do not place hardware breakpoints, use software breakpoints instead.
Alternatively, place a hardware breakpoint on the instruction before the memory
access instruction and then single step over the memory access instruction.
Workaround/fix
The same PID should not be assigned to more than one channel.
Fix/Workaround
After a Software Reset, the register TWI RHR must be read.
AT32UC3A
80
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