P89LPC9151 NXP [NXP Semiconductors], P89LPC9151 Datasheet
P89LPC9151
Related parts for P89LPC9151
P89LPC9151 Summary of contents
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... V byte-erasable flash with 8-bit ADC Rev. 02 — 9 February 2010 1. General description The P89LPC9151/9161/9171 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the device in order to reduce component count, board space, and system cost ...
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... Programmable port output configuration options: quasi-bidirectional, open drain, push-pull, input-only. High current sourcing/sinking (20 mA I/O pins on the P89LPC9151, 3 I/O pins on the P89LPC9161 and 5 I/O pins on the P89LPC9171. All other port pins have high sinking capability (20 mA). A maximum limit is specified for the entire chip. ...
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... P89LPC9151FDH P89LPC9161FDH P89LPC9171FDH 3.1 Ordering options Table 2. Type number P89LPC9151FDH P89LPC9161FDH P89LPC9171FDH P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 Ordering information Package Name Description TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm TSSOP16 plastic thin shrink small outline package ...
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... CONFIGURABLE I/O P0[5:0] CONFIGURABLE I/O KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE OSCILLATOR DIVIDER external clock input OSCILLATOR Fig 1. Block diagram (P89LPC9151) P89LPC9151_61_71_2 Product data sheet HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU internal bus PORT 1 PORT 0 CPU clock ON-CHIP RC ON-CHIP RC OSCILLATOR WITH CLOCK DOUBLER Rev. 02 — ...
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... Product data sheet HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU internal bus PORT 2 PORT 1 PORT 0 CPU clock ON-CHIP RC ON-CHIP RC OSCILLATOR WITH CLOCK DOUBLER Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC UART ADC1/DAC1 SPI REAL TIME CLOCK/ SYSTEM TIMER TIMER 0 TIMER 1 ...
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... Product data sheet HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU internal bus PORT 2 PORT 1 PORT 0 CPU clock ON-CHIP RC OSCILLATOR ON-CHIP RC WITH CLOCK DOUBLER Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC UART ADC1/DAC1 REAL TIME CLOCK/ SYSTEM TIMER TIMER 0 TIMER 1 ANALOG ...
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... NXP Semiconductors 5. Functional diagram KBI0 AD10 KBI1 AD11 KBI2 AD12 KBI3 AD13 DAC1 KBI4 CLKIN KBI5 Fig 4. Functional diagram (P89LPC9151) KBI1 AD10 KBI2 AD11 AD12 KBI3 AD13 DAC1 KBI4 CLKIN KBI5 Fig 5. Functional diagram (P89LPC9161) P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 V DD ...
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... KBI1 AD11 KBI2 AD12 KBI3 AD13 DAC1 KBI4 CLKIN KBI5 CLKOUT KBI7 Fig 6. Functional diagram (P89LPC9171) P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 V DD CMP2 CIN2B CIN2A CIN1B PORT 0 P89LPC9171 CIN1A CMPREF T1 Rev. 02 — 9 February 2010 8-bit microcontroller with 8-bit ADC V SS TXD ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 7. Fig 8. Fig 9. P89LPC9151_61_71_2 Product data sheet P0.1/CIN2B/KBI1/AD10 1 2 P0.0/CMP2/KBI0 3 P1.5/RST P89LPC9151 P1.4/INT1 5 P1.3/INT0/SDA 6 7 P1.2/T0/SCL P89LPC9151 TSSOP14 pin configuration 1 P0.1/CIN2B/KBI1/AD10 P2.4/SS 2 P1.5/RST P89LPC9161 5 P2.3/MISO 6 P2.2/MOSI P1.3/INT0/SDA 7 P1.2/T0/SCL 8 P89LPC9161 TSSOP16 pin configuration P0.1/CIN2B/KBI1/AD10 1 2 P0.0/CMP2/KBI0 3 P1 ...
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... NXP Semiconductors 6.2 Pin description Table 3. P89LPC9151 Pin description Symbol Pin TSSOP14 P0.0 to P0.5 P0.0/CMP2/ 2 KBI0 P0.1/CIN2B/ 1 KBI1/AD10 P0.2/CIN2A/ 14 KBI2/AD11 P0.3/CIN1B/ 13 KBI3/AD12 P0.4/CIN1A/ 12 KBI4/DAC1/AD13 P0.5/CMPREF/ 11 KBI5 P1.0 to P1.5 P89LPC9151_61_71_2 Product data sheet Type Description I/O Port 0: Port 6-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled ...
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... NXP Semiconductors Table 3. P89LPC9151 Pin description Symbol Pin TSSOP14 P1.0/TXD 9 P1.1/RXD 8 P1.2/T0/SCL 7 P1.3/INT0/SDA 6 P1.4/INT1 5 P1.5/RST [1] Input/output for P1.0 to P1.4. Input for P1.5. P89LPC9151_61_71_2 Product data sheet Type Description I/O P1.0 — Port 1 bit 0. O TXD — Transmitter output for serial port. I/O P1.1 — Port 1 bit 1. ...
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... P1.0 — Port 1 bit 0. O TXD — Transmitter output for serial port. I/O P1.1 — Port 1 bit 1. I RXD — Receiver input for serial port. Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC and Table 16 “Static characteristics” and Table 16 “Static characteristics” for for © ...
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... SPICLK — SPI clock. When configured as master, this pin is output; when configured as slave, this pin is input. I Ground reference. I Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC © NXP B.V. 2010. All rights reserved ...
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... P0.7 — Port 0 bit 7. High current source. I/O T1 — Timer/counter 1 external count input or overflow output. I KBI7 — Keyboard input 7. O CLKOUT — Clock output. Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC and Table 16 “Static characteristics” for © NXP B.V. 2010. All rights reserved ...
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... I Ground reference. I Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC and Table 16 “Static characteristics” for details. for © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 7. Functional description Remark: Please refer to the P89LPC9151/9161/9171 User manual for a more detailed functional description. 7.1 Special function registers Remark: SFR accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. • Accesses to any defined SFR locations must be strictly for the functions for the SFRs. ...
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... Table 6. Special function registers - P89LPC9151 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 ACC* Accumulator E0H ADCON1 A/D control 97H ENBI1 register 1 ADINS A/D input A3H AIN13 select ADMODA A/D mode C0H BNDI1 register A ADMODB ...
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... Table 6. Special function registers - P89LPC9151 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB [2] BRGR1 Baud rate BFH generator 0 rate high BRGCON Baud rate BDH - generator 0 control CMP1 Comparator 1 ACH - control register CMP2 Comparator 2 ADH ...
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... Table 6. Special function registers - P89LPC9151 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address DF 2 I2CON* I C-bus control D8H - register 2 I2DAT I C-bus data DAH register I2SCLH Serial clock DDH generator/SCL duty cycle register high ...
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... Table 6. Special function registers - P89LPC9151 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB KBMASK Keypad 86H interrupt mask register KBPATN Keypad pattern 93H register Bit address 87 P0* Port 0 80H - Bit address 97 P1* Port 1 90H ...
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... Table 6. Special function registers - P89LPC9151 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB RTCH RTC register D2H high RTCL RTC register D3H low SADDR Serial port A9H address register SADEN Serial port B9H address enable ...
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... BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [3] The RSTSRC register reflects the cause of the P89LPC9151 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is x011 0000. ...
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... Table 7. Extended special function registers - P89LPC9151 Name Description SFR Bit functions and addresses addr. BODCFG BOD FFC8H configuration register CLKCON CLOCK Control FFDEH CLKOK register RTCDATH Real-time clock FFBFH data register high RTCDATL Real-time clock FFBEH data register low [1] Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are used to access these extended SFRs ...
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Table 8. Special function registers - P89LPC9161 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 ACC* Accumulator E0H ADCON1 A/D control 97H ENBI1 register 1 ADINS A/D input A3H ...
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Table 8. Special function registers - P89LPC9161 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB [2] BRGR1 Baud rate BFH generator 0 rate high BRGCON Baud rate BDH - generator 0 control ...
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Table 8. Special function registers - P89LPC9161 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address DF 2 I2CON* I C-bus control D8H - register 2 I2DAT I C-bus data DAH ...
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Table 8. Special function registers - P89LPC9161 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB KBMASK Keypad 86H interrupt mask register KBPATN Keypad pattern 93H register Bit address 87 P0* Port 0 ...
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Table 8. Special function registers - P89LPC9161 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB PT0AD Port 0 digital F6H - input disable RSTSRC Reset source DFH - register RTCCON RTC control ...
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Table 8. Special function registers - P89LPC9161 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address 8F TCON* Timer 0 and 1 88H TF1 control TH0 Timer 0 high 8CH TH1 ...
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Table 9. Extended special function registers - P89LPC9161 Name Description SFR Bit functions and addresses addr. BODCFG BOD FFC8H configuration register CLKCON CLOCK Control FFDEH CLKOK register RTCDATH Real-time clock FFBFH data register high RTCDATL Real-time clock FFBEH data register ...
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Table 10. Special function registers - P89LPC9171 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 ACC* Accumulator E0H ADCON1 A/D control 97H ENBI1 register 1 ADINS A/D input A3H ...
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Table 10. Special function registers - P89LPC9171 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB [2] BRGR1 Baud rate BFH generator 0 rate high BRGCON Baud rate BDH - generator 0 control ...
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Table 10. Special function registers - P89LPC9171 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address DF 2 I2CON* I C-bus control D8H - register 2 I2DAT I C-bus data DAH ...
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Table 10. Special function registers - P89LPC9171 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB KBMASK Keypad 86H interrupt mask register KBPATN Keypad pattern 93H register Bit address 87 P0* Port 0 ...
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Table 10. Special function registers - P89LPC9171 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB PT0AD Port 0 digital F6H - input disable RSTSRC Reset source DFH - register RTCCON RTC control ...
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Table 10. Special function registers - P89LPC9171 * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB TMOD Timer 0 and 1 89H T1GATE mode TRIM Internal 96H RCCLK oscillator trim register WDCON Watchdog ...
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Table 11. Extended special function registers - P89LPC9171 Name Description SFR Bit functions and addresses addr. BODCFG BOD FFC8H configuration register CLKCON CLOCK Control FFDEH CLKOK register RTCDATH Real-time clock FFBFH data register high RTCDATL Real-time clock FFBEH data register ...
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... Idle mode, it may be turned off prior to entering Idle, saving additional power. 7.5 On-chip RC oscillator option The P89LPC9151/9161/9171 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7.373 MHz ± room temperature ...
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... Remark: When using P0 clock input option, please make sure that P0.5 is configured as input only mode. 7.8 Clock sources switch on the fly P89LPC9151/9161/9171 can implement clock source switch in any sources of watchdog oscillator, 7 MHz/14 MHz IRC oscillator, or external clock input during code is running. CLKOK bit in CLKCON register is used to indicate the clock switch status. CLKOK is cleared when starting clock source switch and set when completed. Notice that when CLKOK is ‘ ...
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... NXP Semiconductors 7.9 CCLK wake-up delay The P89LPC9151/9161/9171 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus 60 μs to 100 μs. If the clock source is the internal RC oscillator, the delay is 200 μs to 300 μ ...
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... Interrupts The P89LPC9151/9161/9171 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources. The P89LPC9151/9171 supports 13 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port TX, serial port RX, combined serial port RX/TX, brownout detect, watchdog/RTC, I The P89LPC9161 supports 13 interrupt sources: external interrupts 0, timers 0 and 1, ...
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... Note that the arbitration ranking is only used to resolve pending requests of the same priority level. 7.14.1 External interrupt inputs The P89LPC9151 and P89LPC9171 have two external interrupt inputs as well as the Keypad Interrupt function. The P89LPC9161 has one external interrupt input as well as the Keypad Interrupt function These external interrupt inputs are identical to those present on the standard 80C51 microcontrollers ...
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... NXP Semiconductors RTCF ERTC (RTCCON.1) WDOVF (P89LPC9161) ENADCI1 ADCI1 ENBI1 BNDI1 Fig 11. Interrupt sources, interrupt enables, and power-down wake-up sources P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 IE0 EX0 IE1 EX1 BOIF EBO KBIF EKBI EWDRT CMF2 CMF1 EC EA (IE0.7) TF0 ET0 TF1 ...
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... NXP Semiconductors 7.15 I/O ports The P89LPC9151 has two I/O ports: Port 0 and Port 1. Ports 0 and 1 are both 6-bit ports. The P89LPC9161/9171 has three I/O ports: Port 0, Port 1 and Port 2. Ports 0 is 5-bit ports in the P89LPC9161 and 7-bit ports in the P89LPC9171, Port 1 is 5-bit ports in the P89LPC9161 and 6-bit ports in the P89LPC9171, Port 2 is 4-bit ports in the P89LPC9161 and 1-bit port in the P89LPC9171 ...
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... The P89LPC9151/9161/9171 device, but the pins are 5 V tolerant. In quasi-bidirectional mode user applies the pin, there will be a current flowing from the pin to V quasi-bidirectional mode is discouraged ...
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... NXP Semiconductors Every output on the P89LPC9151/9161/9171 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals ...
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... NXP Semiconductors 7.17.2 Power-down mode The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC9151/9161/9171 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the data retention supply voltage V entered. SFR contents are not guaranteed after highly recommended to wake-up the processor via reset in this case ...
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... For any other reset, previously set flag bits that have not been cleared will remain set. 7.18.1 Reset vector Following reset, the P89LPC9151/9161/9171 will fetch instructions from either address 0000H or the Boot address. The Boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00H ...
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... RTC/system timer The P89LPC9151/9161/9171 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down. The RTC can be a wake- interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter ...
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... Section 7.21.5 “Baud rate generator and 7.21.5 Baud rate generator and selection The P89LPC9151/9161/9171 enhanced UART has an independent baud rate generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate ...
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... C-bus interface that supports data transfers C-bus P1.3/SDA P1.2/SCL P89LPC9151/9161/ 9171 2 C-bus configuration Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Figure 13. The P89LPC9151/9161/9171 OTHER DEVICE OTHER DEVICE 2 2 WITH I C-BUS WITH I C-BUS INTERFACE INTERFACE 002aae576 ...
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... NXP Semiconductors P1.3/SDA P1.2/SCL Fig 14. I P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 P1.3 INPUT FILTER OUTPUT STAGE INPUT FILTER OUTPUT STAGE timer 1 overflow P1.2 I2CON I2SCLH I2SCLL status bus I2STAT 2 C-bus serial interface block diagram Rev. 02 — 9 February 2010 8-bit microcontroller with 8-bit ADC ...
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... Product data sheet 8-BIT SHIFT REGISTER READ DATA BUFFER SPI clock (master) CLOCK LOGIC MSTR SPEN SPI CONTROL REGISTER SPI internal data bus Figure 16 Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC PIN CONTROL LOGIC clock S M through Figure 18 ...
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... NXP Semiconductors 7.23.1 Typical SPI configurations Fig 16. SPI single master single slave configuration Fig 17. SPI dual device configuration, where either can be a master or a slave P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 master MISO 8-BIT SHIFT MOSI REGISTER SPICLK SPI CLOCK PORT GENERATOR master ...
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... Fig 18. SPI single master multiple slaves configuration 7.24 Analog comparators Two analog comparators are provided on the P89LPC9151/9161/9171. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable inputs) is greater than the negative input (selectable from a pin or an internal reference voltage) ...
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... This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via PCONA.5, or put the device in Total Power-down mode. P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 CP1 OE1 comparator 1 CO1 change detect ...
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... Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few μ few seconds. Please refer to the P89LPC9151/9161/9171 User manual for more details. P89LPC9151_61_71_2 Product data sheet ...
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... Flash program memory 7.28.1 General description The P89LPC9151/9161/9171 flash memory provides in-circuit electrical erasure and programming. The flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any flash sector (256 bytes) or page (16 bytes). The Chip Erase operation will erase the entire program memory ...
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... Flash organization The program memory consists of eight 256-byte sectors on the P89LPC9151/9161/9171 devices. Each sector can be further divided into 16-byte pages. In addition to sector erase, page erase, and byte erase, a 16-byte page register is included which allows from 1 byte to 16 bytes of a given page to be programmed at the same time, substantially reducing overall programming time ...
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... UCFG1 and UCFG2. Please see the P89LPC9151/9161/9171 User’s Manual for additional details. 7.30 User sector security bytes There are 8 User Sector Security Bytes on the P89LPC9151/9161/9171. Each byte corresponds to one sector. Please see the P89LPC9151/9161/9171 User manual for additional details. ...
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... Any combination of the four input channels can be selected for conversion. A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 comp INPUT MUX DAC1 Rev. 02 — ...
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... MSBs of the conversion meet the interrupt criteria (i.e., outside the boundary limits) an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Rev. 02 — 9 February 2010 © NXP B.V. 2010. All rights reserved. ...
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... Idle mode when the conversion is completed if the A/D interrupt is enabled. In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D is enabled, it will consume power. Power can be reduced by disabling the A/D. P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC Rev. 02 — 9 February 2010 © NXP B.V. 2010. All rights reserved ...
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... Parameters are valid over ambient temperature range unless otherwise specified. All voltages are with respect to V otherwise noted. [2] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. Fig 22. Frequency versus supply voltage P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 [1] Conditions on XTAL1, XTAL2; pin to V except XTAL1, XTAL2; pin ...
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... OH V voltage on any other pin n C input capacitance iss I LOW-level input current IL I input leakage current LI I HIGH-LOW transition THL current P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 Conditions MHz DD osc MHz DD osc MHz DD osc MHz ...
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... Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is highest when V is approximately P89LPC9151_61_71_2 Product data sheet …continued Conditions pin RST Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC [1] Min Typ 10 - 1.11 1.23 - ...
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... DD(oper 2.4 2.8 Test conditions: normal mode, code while(1) {} executed from on-chip flash; using an external clock. versus frequency at −40 °C DD(oper) Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC 3.2 V (V) DD 3.2 V (V) DD 002aae363 18 MHz 12 MHz 8 MHz 6 MHz 4 MHz ...
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... Test conditions: idle mode entered executing code from on-chip flash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer. versus frequency at +25 °C DD(idle) Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC 3 ...
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... Test conditions: idle mode entered executing code from on-chip flash; using an external clock with no active peripherals, with the following functions disabled: real-time clock and watchdog timer. versus frequency at +85 °C DD(idle) Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC 3 ...
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... DD(pd 0.8 0.4 0.0 2.4 2.8 Test conditions: Total power-down mode, using internal RC oscillator with the following functions disabled: comparators, brownout detect, real-time clock, and watchdog timer. versus V DD(tpd) DD Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC 3.2 V (V) DD 3.2 V (V) DD 002aae369 (1) (2) (3) 3.6 002aae370 ...
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... Product data sheet 0.2 0.1 0 −0.1 −0.2 2.4 2.8 Central frequency of internal RC oscillator = 7.3728 MHz 0.2 0.1 0 −0.1 −0.2 2.4 2.8 Note: Central frequency of internal RC oscillator = 7.3728 MHz Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC 3 +25 °C DD 3 −40 °C DD 002aae344 3.6 002aae346 3.6 © NXP B.V. 2010. All rights reserved. ...
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... Product data sheet 0.2 0 −0.2 −0.4 −0.6 2.4 2.8 Central frequency of internal RC oscillator = 7.3728 MHz 2.5 1.5 0.5 −0.5 −1.5 2.4 2.8 Central frequency of watchdog oscillator = 400 kHz Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC 3 +85 °C DD 3 +25 °C DD 002aae347 3.6 002aae348 3.6 © NXP B.V. 2010. All rights reserved. ...
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... Product data sheet 0.5 −0.5 −1.5 −2.5 −3.5 2.4 2.8 Central frequency of watchdog oscillator = 400 kHz 1.5 0.5 −0.5 −1.5 −2.5 2.4 2.8 Central frequency of watchdog oscillator = 400 kHz Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC 3 −40 °C DD 3 +85 °C DD 002aae349 3.6 002aae350 3.6 © ...
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... BOD EEPROM/FLASH V trip voltage trip [1] Typical ratings are not guaranteed. The values listed are at room temperature Fig 37. BOD interrupt/reset characteristics P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 Conditions falling stage BOICFG1, BOICFG0 = 01 BOICFG1, BOICFG0 = 10 BOICFG1, BOICFG0 = 11 rising stage BOICFG1, BOICFG0 = 01 BOICFG1, BOICFG0 = 10 ...
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... XHDV rising edge time SPI interface f SPI operating frequency SPI slave master P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 Conditions nominal f = 7.3728 MHz 7.189 trimmed to ± °C; clock T amb doubler option = OFF (default) nominal f = 14.7456 MHz; 14.378 clock doubler option = ON ...
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... MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 …continued Conditions see Figure 40, 41, 42 see ...
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... SPI interface f SPI operating frequency SPI slave master T SPI cycle time SPICYC slave master P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 Conditions nominal f = 7.3728 MHz trimmed to ± °C; clock T amb doubler option = OFF (default) nominal f = 14.7456 MHz; clock doubler option = °C T ...
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... MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 …continued Conditions see Figure 42, 43 see Figure ...
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... SPICLKH t t SPIF SPIR t SPICLKL t SPICLKH t t SPIDSU SPIDH MSB/LSB SPIDV SPIOH master MSB/LSB out Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC t CHCX t CLCH T cy(clk) 002aaa907 = 200 mV valid valid valid t SPIR LSB/MSB in t SPIDV master LSB/MSB out ...
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... SPICLKL t SPICLKH t t SPIOH SPIOH t t SPIDV SPIDV slave MSB/LSB out t t SPIDH SPIDSU MSB/LSB in Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC t SPIR LSB/MSB SPIOH SPIDV master LSB/MSB out 002aaa909 t SPILAG t SPIOH slave LSB/MSB out not defined t ...
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... IC CMRR common-mode rejection ratio t total response time res(tot) t chip enable to output valid time (CE-OV) I input leakage current LI [1] This parameter is characterized, but not tested in production. P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 T SPICYC t t SPIF SPIR t SPICLKL t SPICLKH t SPIR t SPICLKL t SPICLKH ...
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... ADC clock cycle time cy(ADC) t ADC conversion time ADC start trigger 1 2 adc_clk clk serial_data_out ADCDATA_REG Fig 44. ADC conversion timing P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 Ω . Conditions 0 kHz to 100 kHz ADC enabled Rev. 02 — 9 February 2010 8-bit microcontroller with 8-bit ADC ...
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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. Fig 45. ADC characteristics P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 (2) 1 LSB (ideal (LSB ) IA ideal Rev. 02 — 9 February 2010 8-bit microcontroller with 8-bit ADC offset ...
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... Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT402-1 Fig 46. TSSOP14 package outline (SOT402-1) P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 2.5 scale ...
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... Product data sheet 2.5 scale (1) ( 0.30 0.2 5.1 4.5 0.65 0.19 0.1 4.9 4.3 REFERENCES JEDEC JEITA MO-153 Rev. 02 — 9 February 2010 P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN ...
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... RAM RC RTC SAR SCL SDA SFR SPI UART P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 Abbreviations Description Analog to Digital Converter Brownout Detection Central Processing Unit Digital to Analog Converter Electrically Erasable Programmable Read-Only Memory Erasable Programmable Read-Only Memory ElectroMagnetic Interference Internal RC Least Significant Bit ...
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... Changed data sheet status to "Product data sheet". P89LPC9151_61_71_1 20091209 P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 Data sheet status Change notice Product data sheet - Preliminary data sheet - Rev. 02 — 9 February 2010 8-bit microcontroller with 8-bit ADC Supersedes P89LPC9151_61_71_1 - © NXP B.V. 2010. All rights reserved ...
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... P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 [3] Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. ...
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... NXP Semiconductors’ product specifications. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — ...
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... Power reduction modes . . . . . . . . . . . . . . . . . 46 7.17.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.17.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . 47 7.17.3 Total Power-down mode . . . . . . . . . . . . . . . . . 47 7.18 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.18.1 Reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.19 Timers/counters 0 and P89LPC9151_61_71_2 Product data sheet P89LPC9151/9161/9171 8-bit microcontroller with 8-bit ADC 7.19.1 Mode 7.19.2 Mode 7.19.3 Mode 7.19.4 Mode 7.19.5 Mode 7.19.6 Timer overflow toggle output . . . . . . . . . . . . . 49 7.20 RTC/system timer . . . . . . . . . . . . . . . . . . . . . 49 7 ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: P89LPC9151_61_71_2 All rights reserved. Date of release: 9 February 2010 ...