P89LPC9151 NXP [NXP Semiconductors], P89LPC9151 Datasheet - Page 63
P89LPC9151
Manufacturer Part Number
P89LPC9151
Description
8-bit microcontroller with accelerated two-clock 80C51 core, 2 kB 3 V byte-erasable flash with 8-bit ADC
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.P89LPC9151.pdf
(91 pages)
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NXP Semiconductors
P89LPC9151_61_71_2
Product data sheet
8.7 DAC output to a port pin with high output impedance
8.8 Clock divider
8.9 Power-down and Idle mode
criteria, the boundary limits will again be compared after all 8 bits have been converted.
The boundary status register (BNDSTA0) flags the channels which caused a boundary
interrupt.
The DAC block of ADC1 can be output to a port pin. In this mode, the AD1DAT3 register is
used to hold the value fed to the DAC. After a value has been written to the DAC (written
to AD1DAT3), the DAC output will appear on the channel 3 pin.
The ADC requires that its internal clock source be in the range of 320 kHz to 8 MHz to
maintain accuracy. A programmable clock divider that divides the clock from 1 to 8 is
provided for this purpose.
In Idle mode the A/C converter, if enabled, will continue to function and can cause the
device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled.
In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D is
enabled, it will consume power. Power can be reduced by disabling the A/D.
Rev. 02 — 9 February 2010
P89LPC9151/9161/9171
8-bit microcontroller with 8-bit ADC
© NXP B.V. 2010. All rights reserved.
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