P80C31SFPN PHILIPS [NXP Semiconductors], P80C31SFPN Datasheet - Page 15

• Manufacturer Part Number: P80C31SFPN
• Description: 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless low voltage 2.7V.5.5V, low power, high speed 33 MHz
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are trended
as don’t-cares. In most cases, interpreting the don’t-cares as ones,
the broadcast address will be FF hexadecimal.
2000 Jan 20
NOTE:
*SMOD0 is located at PCON6.
**f
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33 MHz)
OSC
Symbol
FE
SM0
SM1
SM2
REN
TB8
RB8
Tl
Rl
= oscillator frequency
Bit Addressable
Bit:
Function
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
Serial Port Mode Bit 1
SM0
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
0
0
1
1
SCON Address = 98H
(SMOD0 = 0/1)*
SM0/FE
7
SM1
0
1
0
1
SM1
Mode
6
0
1
2
3
Figure 7. SCON: Serial Port Control Register
SM2
5
Description
shift register
8-bit UART
9-bit UART
9-bit UART
REN
4
Baud Rate**
f
variable
f
variable
OSC
OSC
15
TB8
/12
/64 or f
3
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR
address 0B9H) are leaded with 0s. This produces a given address
of all “don’t cares” as well as a Broadcast address of all “don’t
cares”. This effectively disables the Automatic Addressing mode and
allows the microcontroller to use standard 80C51 type UART drivers
which do not make use of this feature.
OSC
RB8
/32
2
Tl
1
80C51/87C51/80C31
Rl
0
Reset Value = 0000 0000B
Product specification
SU00043