LPC2141_08 NXP [NXP Semiconductors], LPC2141_08 Datasheet - Page 18

• Manufacturer Part Number: LPC2141_08
• Description: Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, USB 2.0 full-speed device, 10-bit ADC and DAC
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC2141_42_44_46_48_4
Product data sheet
6.11.1 Features
6.12.1 Features
6.12 I
6.13 SPI serial I/O controller
The LPC2141/42/44/46/48 each contain two I
The I
(SCL), and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver or a transmitter with the
capability to both receive and send information (such as memory)). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
The I
(Fast I
The LPC2141/42/44/46/48 each contain one SPI controller. The SPI is a full duplex serial
interface, designed to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.
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C-bus serial I/O controller
16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Transmission FIFO control enables implementation of software (XON/XOFF) flow
control on both UARTs.
LPC2144/46/48 UART1 equipped with standard modem interface signals. This
module also provides full support for hardware flow control (auto-CTS/RTS).
Compliant with standard I
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
2
C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line
C-bus implemented in LPC2141/42/44/46/48 supports bit rates up to 400 kbit/s
2
C-bus).
2
C-bus can be used for test and diagnostic purposes.
Rev. 04 — 17 November 2008
2
C-bus interface.
LPC2141/42/44/46/48
2
Single-chip 16-bit/32-bit microcontrollers
C-bus controllers.
2
C-bus is a multi-master bus, it can be
© NXP B.V. 2008. All rights reserved.
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