LPC2364FB100 PHILIPS [NXP Semiconductors], LPC2364FB100 Datasheet - Page 29

• Manufacturer Part Number: LPC2364FB100
• Description: Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
LPC2364_66_68_1
Preliminary data sheet
7.24.4.3 Power-down mode
7.24.4.4 Deep power-down mode
7.24.4.5 Power domains
On the wake-up of sleep mode, if the IRC was used before entering sleep mode, the code
execution and peripherals activities will resume after 4 cycles expire. If the main external
oscillator was used, the code execution will resume when 4096 cycles expire.
The customers need to reconfigure the PLL and clock dividers accordingly.
Power-down mode does everything that Sleep mode does, but also turns off the IRC
oscillator and the Flash memory. This saves more power, but requires waiting for
resumption of Flash operation before execution of code or data access in the Flash
memory can be accomplished.
On the wake-up of power-down mode, if the IRC was used before entering power-down
mode, it will take IRC 60 µs to start-up. After this 4 IRC cycles will expire before the code
execution can then be resumed if the code was running from SRAM. In the meantime, the
flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 µs Flash
start-up time. When it times out, access to the Flash will be allowed. The customers need
to reconfigure the PLL and clock dividers accordingly.
Deep power-down mode is like Power-down mode, but the on-chip regulator that supplies
power to internal logic is also shut off. This produces the lowest possible power
consumption without actually removing power from the entire chip. Since Deep
power-down mode shuts down the on-chip logic power supply, there is no register or
memory retention, and resumption of operation involves the same activities as a full-chip
reset.
If power is supplied to the LPC2364/66/68 during Deep power-down mode, wake-up can
be caused by external Reset.
While in Deep power-down mode, external device power may be removed. In this case,
the LPC2364/66/68 will start up when external power is restored.
Essential data may be retained through Deep power-down mode (or through complete
powering off of the chip) by storing data in the Battery RAM, as long as the external power
to the VBAT pin is maintained.
The LPC2364/66/68 provides two independent power domains that allow the bulk of the
device to have power removed while maintaining operation of the Real Time Clock and
the Battery RAM.
The 3.3V (V
These pins provide the power for the CPU and most of the peripherals. If power is
removed from the VDD pins, the CPU and related peripherals stop.
The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
DD(3V3)
) pins power both the on-chip DC-DC converter and the I/O pads.
Rev. 01 — 22 September 2006
LPC2364/2366/2368
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Fast communication chip
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