P87C660X2 PHILIPS [NXP Semiconductors], P87C660X2 Datasheet - Page 64

• Manufacturer Part Number: P87C660X2
• Description: 80C51 8-bit microcontroller family
• Manufacturer: PHILIPS [NXP Semiconductors]

1. L = Level activated
2. T = Transition activated
1. L = Level activated
2. T = Transition activated
Philips Semiconductors
Interrupt Priority Structure
The P8xC660X2/661X2 has an 8/9 source four-level interrupt
structure (see Table 15).
There are 4 SFRs associated with the four-level interrupt. They are
the IE, IEN1, IP, and IPH. (See Figures 31, 32, and 33.) The IPH
(Interrupt Priority High) register makes the four-level interrupt
structure possible. The IPH is located at SFR address B7H.
Table 15.
NOTES:
Table 16.
NOTES:
The priority scheme for servicing the interrupts is the same as that
for the 80C51, except there are four interrupt levels rather than two
as on the 80C51. An interrupt will be serviced as long as an interrupt
of equal or higher priority is not already being serviced. If an
interrupt of equal or higher level priority is being serviced, the new
2003 Oct 02
80C51 8-bit microcontroller family
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I
SIO1 (I2C)
SIO2 (I2C)
SIO1 (I2C)
SOURCE
SOURCE
PCA
PCA
SP
SP
X0
T0
X1
T1
T2
X0
T0
X1
T1
T2
Interrupt Table P8xC661X2
Interrupt Table P8xC662X2
2
C interfaces
POLLING PRIORITY
POLLING PRIORITY
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
16 KB OTP/ROM, 512B
REQUEST BITS
REQUEST BITS
TF2, EXF2
TF2, EXF2
CF, CCFn
CF, CCFn
n = 0–4
n = 0–4
RI, TI
RI, TI
TP0
TF1
TP0
TF1
IE0
IE1
IE0
IE1
64
–
–
–
The function of the IPH SFR, when combined with the IP SFR,
determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
Table 14.
interrupt will wait until it is finished before being serviced. If a lower
priority level interrupt is being serviced, it will be stopped and the
new interrupt serviced. When the new interrupt is finished, the lower
priority level interrupt that was stopped will be completed.
IPH.x
PRIORITY BITS
0
0
1
1
HARDWARE CLEAR?
HARDWARE CLEAR?
N (L)
N (L)
N (L) Y (T)
N (L) Y (T)
IP.x
0
1
0
1
1
1
N
N
Y
Y
N
N
N
N
Y
Y
N
N
N
Y (T)
Y (T)
Level 0 (lowest priority)
Level 1
Level 2
Level 3 (highest priority)
2
2
P8xC660X2/661X2
INTERRUPT PRIORITY LEVEL
INTERRUPT PRIORITY LEVEL
VECTOR ADDRESS
VECTOR ADDRESS
2BH
0BH
1BH
3BH
2BH
0BH
1BH
3BH
03H
43H
13H
23H
33H
03H
13H
23H
33H
Product data