P87C660X2 PHILIPS [NXP Semiconductors], P87C660X2 Datasheet - Page 84

• Manufacturer Part Number: P87C660X2
• Description: 80C51 8-bit microcontroller family
• Manufacturer: PHILIPS [NXP Semiconductors]

1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all outputs = 80 pF
3. Interfacing the microcontroller to devices with float time up to 45 ns is permitted. This limited bus contention will not cause damage to port 0
4. Parts are guaranteed by design to operate down to 0 Hz.
5. Below 16 MHz this parameter is 8 t
Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE, 2.7 V TO 5.5 V OPERATION)
T
NOTES:
2003 Oct 02
Symbol
1/t
t
t
t
t
t
t
t
t
t
t
t
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
External Clock
t
t
t
t
Shift register
t
t
t
t
t
amb
LHLL
AVLL
LLAX
LLIV
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
WHQX
QVWH
RLAZ
WHLH
CHCX
CLCX
CLCH
CHCL
XLXL
QVXH
XHQX
XHDX
XHDV
80C51 8-bit microcontroller family
RAM, low voltage (2.7 to 5.5 V), low power, high speed (30/33
MHz), two 400KB I
CLCL
drivers.
= 0 C to +70 C or –40 C to +85 C ; V
Figure
55
50
50
50
50
50
50
50
50
50
50
50
51
52
51
51
51
51
51
51, 52
51, 52
52
52
52
51
51, 52
55
55
55
55
54
54
54
54
54
2
Parameter
Oscillator frequency
ALE pulse width
Address valid to ALE LOW
Address hold after ALE LOW
ALE LOW to valid instruction in
ALE LOW to PSEN LOW
PSEN pulse width
PSEN LOW to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN LOW to address float
RD pulse width
WR pulse width
RD LOW to valid data in
Data hold after RD
Data float after RD
ALE LOW to valid data in
Address to valid data in
ALE LOW to RD or WR LOW
Address valid to WR LOW or RD LOW
Data valid to WR transition
Data hold after WR
Data valid to WR HIGH
RD LOW to address float
RD or WR HIGH to ALE HIGH
High time
Low time
Rise time
Fall time
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
C interfaces
CLCL
– 133.
CC
16 KB OTP/ROM, 512B
= 2.7 V to 5.5 V, V
5
SS
= 0 V
84
1,2,3,4
Limits
MIN
0
2t
t
t
3 t
0
6 t
6 t
0
3 t
4 t
t
t
7 t
t
0.32 t
0.32 t
12 t
10 t
2 t
0
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
–25
–15
–30
–20
–15
–10
–15
–15
–25
–25
–20
–20
–10
–15
–25
MAX
16
4 t
3 t
t
5 t
10
5 t
2 t
8 t
9 t
3 t
0
t
t
t
5
5
10 t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
–10
+15
– t
– t
–55
–55
–50
–50
–20
–55
–50
+20
CLCX
CHCX
–133
P8xC660X2/661X2
16 MHz Clock
MIN
115
47.5
37.5
47.5
172.5
0
350
350
0
167.5
230
32.5
42.5
427.5
47.5
750
600
110
0
MAX
195
132.5
52.5
262.5
10
262.5
105
445
512.5
207.5
0
77.5
492
Product data
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns