LPC3230 NXP [NXP Semiconductors], LPC3230 Datasheet - Page 27

• Manufacturer Part Number: LPC3230
• Description: 16/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go, and EMC memory interface
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC3220_30_40_50_1
Preliminary data sheet
7.6.1 General Purpose DMA (GPDMA) controller
7.6.2 Ethernet MAC
7.6 AHB master peripherals
The LPC3220/30/40/50 implements four AHB master peripherals, which include a
General Purpose Direct Memory Access (GPDMA) controller, a 10/100 Ethernet Media
Access Controller (MAC), a Universal Serial Bus (USB) controller, and an LCD controller.
Each of these four peripherals contain an integral DMA controller optimized to support the
performance demands of the peripheral.
The GPDMA controller allows peripheral-to memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receive. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the same AHB master, or one area by each master. The DMA
controller supports the following peripheral device transfers.
The DMA controls eight DMA channels with hardware prioritization. The DMA controller
interfaces to the system via two AHB bus masters, each with a full 32-bit data bus width.
DMA operations may be set up for 8-bit, 16-bit, and 32-bit data widths, and can be either
big-endian or little-endian. Incrementing or non-incrementing addressing for source and
destination are supported, as well as programmable DMA burst size. Scatter or gather
DMA is supported through the use of linked lists. This means that the source and
destination areas do not have to occupy contiguous areas of memory.
The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC
designed to provide optimized performance through the use of DMA hardware
acceleration. Features include a generous suite of control registers, half or full duplex
operation, flow control, control frames, hardware acceleration for transmit retry, receive
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– extended wait
Power-saving modes dynamically control MPMCCKEOUT and MPMCCLKOUT.
Dynamic memory self-refresh mode supported by software.
Controller supports 2 k, 4 k, and 8 k row address synchronous memory parts. That is,
typical 512 MB, 256 MB, 128 MB, and 16 MB parts, with 8, 16, or 32 data bits per
device.
Two reset domains enable dynamic memory contents to be preserved over a soft
reset.
This controller does not support synchronous static memory devices (burst mode
devices).
Secure Digital (SD) Memory interface
High-speed UARTs
I
SPI1 and SPI2 interfaces
SSP0 and SSP1 interfaces
Memory
2
S0 and I
2
S1 ports
Rev. 01 — 6 February 2009
LPC3220/30/40/50
16/32-bit ARM microcontrollers
© NXP B.V. 2009. All rights reserved.
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