LPC1754 NXP [NXP Semiconductors], LPC1754 Datasheet - Page 36

• Manufacturer Part Number: LPC1754
• Description: 32-bit ARM Cortex-M3 MCU; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
LPC1759_58_56_54_52_51_4
Product data sheet
7.30.5 AHB multilayer matrix
7.30.6 External interrupt inputs
7.30.7 Memory mapping control
7.31 Emulation and debugging
The LPC1759/58/56/54/52/51 use an AHB multilayer matrix. This matrix connects the
instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash
memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access
all of these memories. The peripheral DMA controllers, Ethernet (LPC1758 only) and
USB, can access all SRAM blocks. Additionally, the matrix connects the CPU system bus
and all of the DMA controllers to the various peripheral functions.
The LPC1759/58/56/54/52/51 include up to 30 edge sensitive interrupt inputs combined
with one level sensitive external interrupt input as selectable pin function. The external
interrupt input can optionally be used to wake up the processor from Power-down mode.
The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the NVIC.
The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address
space. The vector table must be located on a 128 word (512 byte) boundary because the
NVIC on the LPC1759/58/56/54/52/51 is configured for 128 total interrupts.
Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and
trace functions are supported in addition to a standard JTAG debug and parallel trace
functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four
watch points.
Rev. 04 — 26 January 2010
LPC1759/58/56/54/52/51
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2010. All rights reserved.
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